48 lines
1.8 KiB
Tcl
48 lines
1.8 KiB
Tcl
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## FIFO depth is 18Mb - 1M samples
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set dac_fifo_name axi_adrv9009_dacfifo
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set dac_fifo_address_width 17
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set dac_data_width 128
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set dac_dma_data_width 128
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## NOTE: With this configuration the #36Kb BRAM utilization is at ~57%
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source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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ad_mem_hp0_interconnect sys_cpu_clk sys_ps8/S_AXI_HP0
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source ../common/adrv9009_bd.tcl
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ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_parameter axi_adrv9009_rx_dma CONFIG.FIFO_SIZE 32
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ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.FIFO_SIZE 32
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ad_ip_parameter axi_adrv9009_tx_dma CONFIG.FIFO_SIZE 32
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ad_ip_instance clk_wiz dma_clk_wiz
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ad_ip_parameter dma_clk_wiz CONFIG.PRIMITIVE MMCM
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ad_ip_parameter dma_clk_wiz CONFIG.RESET_TYPE ACTIVE_LOW
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ad_ip_parameter dma_clk_wiz CONFIG.USE_LOCKED false
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ad_ip_parameter dma_clk_wiz CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 332.9
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ad_ip_parameter dma_clk_wiz CONFIG.PRIM_SOURCE No_buffer
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ad_connect sys_cpu_clk dma_clk_wiz/clk_in1
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ad_connect sys_cpu_resetn dma_clk_wiz/resetn
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ad_connect sys_dma_clk dma_clk_wiz/clk_out1
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ad_connect sys_dma_rstgen/ext_reset_in sys_rstgen/peripheral_reset
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ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.XCVR_TYPE 2
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ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.XCVR_TYPE 2
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ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.XCVR_TYPE 2
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ad_ip_parameter util_adrv9009_xcvr CONFIG.XCVR_TYPE 2
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ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 80
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ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_REFCLK_DIV 1
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ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.DEVICE_TYPE 2
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ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.DEVICE_TYPE 2
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