105 lines
3.3 KiB
Verilog
105 lines
3.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_lvds_out #(
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parameter DEVICE_TYPE = 0,
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parameter SINGLE_ENDED = 0,
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parameter IODELAY_ENABLE = 0,
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parameter IODELAY_CTRL = 0,
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parameter IODELAY_GROUP = "dev_if_delay_group") (
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// data interface
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input tx_clk,
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input tx_data_p,
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input tx_data_n,
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output tx_data_out_p,
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output tx_data_out_n,
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// delay-data interface
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input up_clk,
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input up_dld,
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input [ 4:0] up_dwdata,
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output [ 4:0] up_drdata,
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// delay-cntrl interface
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input delay_clk,
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input delay_rst,
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output delay_locked);
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// defaults
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assign up_drdata = 5'd0;
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assign delay_locked = 1'b1;
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// instantiations
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generate
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if (DEVICE_TYPE == 0) begin
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alt_ddio_out i_tx_data_oddr (
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.ck (tx_clk),
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.din ({tx_data_p, tx_data_n}),
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.pad_out (tx_data_out_p));
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end
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endgenerate
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generate
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if (DEVICE_TYPE == 1) begin
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altddio_out #(.width (1), .lpm_hint ("UNUSED")) i_tx_data_oddr (
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.outclock (tx_clk),
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.datain_h (tx_data_p),
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.datain_l (tx_data_n),
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.dataout (tx_data_out_p),
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.outclocken (1'b1),
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.oe_out (),
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.oe (1'b1),
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.aclr (1'b0),
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.aset (1'b0),
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.sclr (1'b0),
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.sset (1'b0));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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