210 lines
6.6 KiB
Verilog
210 lines
6.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ps/1ps
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module __ad_serdes_clk__ #(
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// parameters
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parameter DEVICE_TYPE = 0,
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parameter DDR_OR_SDR_N = 1,
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parameter SERDES_FACTOR = 8,
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parameter MMCM_OR_BUFR_N = 1,
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parameter MMCM_CLKIN_PERIOD = 1.667,
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parameter MMCM_VCO_DIV = 6,
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parameter MMCM_VCO_MUL = 12.000,
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parameter MMCM_CLK0_DIV = 2.000,
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parameter MMCM_CLK1_DIV = 6) (
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// clock and divided clock
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input rst,
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input clk_in_p,
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input clk_in_n,
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output clk,
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output div_clk,
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output out_clk,
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output loaden,
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output [ 7:0] phase,
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// drp interface
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input up_clk,
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input up_rstn,
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input up_drp_sel,
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input up_drp_wr,
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input [11:0] up_drp_addr,
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input [31:0] up_drp_wdata,
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output [31:0] up_drp_rdata,
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output up_drp_ready,
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output up_drp_locked);
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// local parameter
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localparam ARRIA10 = 0;
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localparam CYCLONE5 = 1;
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// internal registers
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reg up_drp_sel_int = 'd0;
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reg up_drp_rd_int = 'd0;
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reg up_drp_wr_int = 'd0;
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reg [ 8:0] up_drp_addr_int = 'd0;
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reg [31:0] up_drp_wdata_int = 'd0;
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reg [31:0] up_drp_rdata_int = 'd0;
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reg up_drp_ready_int = 'd0;
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reg up_drp_locked_int_m = 'd0;
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reg up_drp_locked_int = 'd0;
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// internal signals
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wire up_drp_reset;
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wire [31:0] up_drp_rdata_int_s;
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wire up_drp_busy_int_s;
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wire up_drp_locked_int_s;
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wire loaden_s;
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wire clk_s;
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// defaults
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assign up_drp_reset = ~up_rstn;
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assign out_clk = div_clk;
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assign up_drp_rdata = up_drp_rdata_int;
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assign up_drp_ready = up_drp_ready_int;
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assign up_drp_locked = up_drp_locked_int;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_drp_sel_int <= 1'b0;
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up_drp_rd_int <= 1'b0;
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up_drp_wr_int <= 1'b0;
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up_drp_addr_int <= 9'd0;
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up_drp_wdata_int <= 32'd0;
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up_drp_rdata_int <= 32'd0;
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up_drp_ready_int <= 1'b0;
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up_drp_locked_int_m <= 1'd0;
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up_drp_locked_int <= 1'd0;
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end else begin
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if (up_drp_sel_int == 1'b1) begin
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if (up_drp_busy_int_s == 1'b0) begin
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up_drp_sel_int <= 1'b0;
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up_drp_rd_int <= 1'b0;
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up_drp_wr_int <= 1'b0;
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up_drp_addr_int <= 9'd0;
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up_drp_wdata_int <= 32'd0;
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up_drp_rdata_int <= up_drp_rdata_int_s;
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up_drp_ready_int <= 1'b1;
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end
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end else if (up_drp_sel == 1'b1) begin
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up_drp_sel_int <= 1'b1;
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up_drp_rd_int <= ~up_drp_wr;
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up_drp_wr_int <= up_drp_wr;
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up_drp_addr_int <= up_drp_addr[8:0];
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up_drp_wdata_int <= up_drp_wdata;
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up_drp_rdata_int <= 32'd0;
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up_drp_ready_int <= 1'b0;
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end else begin
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up_drp_sel_int <= 1'b0;
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up_drp_rd_int <= 1'b0;
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up_drp_wr_int <= 1'b0;
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up_drp_addr_int <= 9'd0;
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up_drp_wdata_int <= 32'd0;
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up_drp_rdata_int <= 32'd0;
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up_drp_ready_int <= 1'b0;
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end
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up_drp_locked_int_m <= up_drp_locked_int_s;
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up_drp_locked_int <= up_drp_locked_int_m;
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end
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end
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generate
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if (DEVICE_TYPE == ARRIA10) begin
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__ad_serdes_clk_1__ i_core (
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.rst_reset (rst),
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.ref_clk_clk (clk_in_p),
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.locked_export (up_drp_locked_int_s),
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.hs_phase_phout (phase),
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.hs_clk_lvds_clk (clk),
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.loaden_loaden (loaden),
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.ls_clk_clk (div_clk),
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.drp_clk_clk (up_clk),
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.drp_rst_reset (up_drp_reset),
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.pll_reconfig_waitrequest (up_drp_busy_int_s),
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.pll_reconfig_read (up_drp_rd_int),
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.pll_reconfig_write (up_drp_wr_int),
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.pll_reconfig_readdata (up_drp_rdata_int_s),
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.pll_reconfig_address (up_drp_addr_int),
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.pll_reconfig_writedata (up_drp_wdata_int));
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end
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endgenerate
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generate
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if (DEVICE_TYPE == CYCLONE5) begin
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assign phase = 8'd0;
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__ad_serdes_clk_1__ i_core (
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.rst_reset (rst),
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.ref_clk_clk (clk_in_p),
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.locked_export (up_drp_locked_int_s),
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.hs_clk_clk (clk_s),
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.loaden_clk (loaden_s),
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.ls_clk_clk (div_clk),
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.drp_clk_clk (up_clk),
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.drp_rst_reset (up_drp_reset),
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.pll_reconfig_waitrequest (up_drp_busy_int_s),
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.pll_reconfig_read (up_drp_rd_int),
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.pll_reconfig_write (up_drp_wr_int),
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.pll_reconfig_readdata (up_drp_rdata_int_s),
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.pll_reconfig_address (up_drp_addr_int[5:0]),
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.pll_reconfig_writedata (up_drp_wdata_int));
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cyclonev_pll_lvds_output #(
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.pll_loaden_enable_disable ("true"),
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.pll_lvdsclk_enable_disable ("true"))
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i_clk_buf (
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.ccout ({loaden_s, clk_s}),
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.loaden (loaden),
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.lvdsclk (clk));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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