255 lines
7.8 KiB
Verilog
255 lines
7.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_mc_speed
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//----------- Ports Declarations -----------------------------------------------
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(
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// physical interface
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input [2:0] position_i,
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output [2:0] position_o,
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output [31:0] speed_o,
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output new_speed_o,
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input [1:0] hall_bemf_i,
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input ref_clk,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [31:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [31:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot
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);
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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reg [31:0] up_rdata = 'd0;
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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//------------------------------------------------------------------------------
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//----------- Wires Declarations -----------------------------------------------
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//------------------------------------------------------------------------------
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// internal clocks & resets
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wire adc_rst;
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire [31:0] speed_data_s;
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wire adc_enable_s;
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wire adc_status_s;
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wire up_rreq_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_adc_common_rdata_s;
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wire up_adc_common_wack_s;
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wire up_adc_common_rack_s;
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wire [31:0] pid_s;
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wire [ 2:0] position_s;
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wire [ 2:0] bemf_s;
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wire [ 2:0] bemf_delayed_s;
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wire new_speed_s;
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wire [ 2:0] bemf_multiplex_s;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign bemf_s = position_s ;
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assign position_o =(hall_bemf_i == 2'b01) ? bemf_delayed_s : position_s;
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assign new_speed_o = new_speed_s;
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assign speed_o = speed_data_s;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk)
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begin
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if(up_rstn == 0)
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begin
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up_rdata <= 'd0;
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up_wack <= 'd0;
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up_rack <= 'd0;
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end else
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begin
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up_rdata <= up_adc_common_rdata_s;
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up_wack <= up_adc_common_wack_s;
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up_rack <= up_adc_common_rack_s;
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end
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end
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// HALL sensors debouncers
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debouncer
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#( .DEBOUNCER_LENGTH(400))
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position_0(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.sig_i(position_i[0]),
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.sig_o(position_s[0]));
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debouncer
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#( .DEBOUNCER_LENGTH(400))
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position_1(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.sig_i(position_i[1]),
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.sig_o(position_s[1]));
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debouncer
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#( .DEBOUNCER_LENGTH(400))
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position_2(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.sig_i(position_i[2]),
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.sig_o(position_s[2]));
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delay_30_degrees delay_30_degrees_i1(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.offset_i(32'h0),
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.position_i(bemf_s),
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.position_o(bemf_delayed_s));
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speed_detector
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#( .AVERAGE_WINDOW(1024),
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.LOG_2_AW(10),
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.SAMPLE_CLK_DECIM(1000))
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speed_detector_inst(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.position_i(position_o),
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.new_speed_o(new_speed_s),
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.current_speed_o(),
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.speed_o(speed_data_s));
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// common processor control
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up_adc_common i_up_adc_common(
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.mmcm_rst(),
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.adc_clk(ref_clk),
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.adc_rst(adc_rst),
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.adc_r1_mode(),
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.adc_ddr_edgesel(),
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.adc_pin_mode(),
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.adc_status(1'b1),
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.adc_sync_status(1'b1),
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.adc_status_ovf(1'b0),
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.adc_status_unf(1'b0),
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.adc_clk_ratio(32'd1),
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.adc_start_code(),
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.adc_sref_sync(),
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.adc_sync(),
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.up_adc_ce(),
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.up_status_pn_err(1'b0),
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.up_status_pn_oos(1'b0),
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.up_status_or(1'b0),
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.up_drp_sel(),
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.up_drp_wr(),
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.up_drp_addr(),
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.up_drp_wdata(),
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.up_drp_rdata(16'd0),
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.up_drp_ready(1'b0),
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.up_drp_locked(1'b0),
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.up_usr_chanmax_out(),
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.up_usr_chanmax_in(8'd1),
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.up_adc_gpio_in(32'h0),
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.up_adc_gpio_out(),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_adc_common_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_adc_common_rdata_s),
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.up_rack (up_adc_common_rack_s));
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// up bus interface
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up_axi i_up_axi(
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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