49 lines
3.5 KiB
Plaintext
49 lines
3.5 KiB
Plaintext
###############################################################################
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## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# ad463x_fmc SPI interface
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set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo] ; ## C11 FMC_LA06_N
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sclk] ; ## G6 FMC_LA00_CC_P
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set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_cs] ; ## G7 FMC_LA00_CC_N
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set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports ad463x_echo_sclk] ; ## D20 FMC_LA17_CC_P
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set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad463x_resetn] ; ## D9 FMC_LA01_CC_N
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set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_busy] ; ## C22 FMC_LA18_CC_P
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set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_cnv] ; ## D8 FMC_LA01_CC_P
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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_ext_clk] ; ## H4 FMC_CLK0_P
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set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[0]}] ; ## G12 FMC-LA08_P
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set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[1]}] ; ## G13 FMC-LA08_N
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set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports max17687_rst] ; ## H13 FMC-LA07_P
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set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports max17687_en] ; ## H14 FMC-LA07_N
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set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports max17687_sync_clk] ; ## D21 FMC-LA17_N_CC
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# external clock, that drives the CNV generator, must have a maximum 100 MHz frequency
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create_clock -period 10.000 -name cnv_ext_clk [get_ports ad463x_ext_clk]
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# SCLK echod clock, tuned to 80 MHz //, phase shifted with 30% (aprox. 4ns)
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create_clock -period 12.500 -name ECHOSCLK_clk [get_ports ad463x_echo_sclk]
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# rename auto-generated clock for SPIEngine to spi_clk - 160MHz
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# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
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create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
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# create a generated clock for SCLK - fSCLK=spi_clk/2 - 80MHz
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create_generated_clock -name SCLK_clk -source [get_pins -hier -filter name=~*sclk_reg/C] -edges {1 3 5} [get_ports ad463x_spi_sclk]
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# output delay for MOSI line (SDI for the device)
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#
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# tHSDI and tSSDI is 1.5ns
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set_output_delay -clock [get_clocks SCLK_clk] -max 1.500 [get_ports ad463x_spi_sdo]
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set_output_delay -clock [get_clocks SCLK_clk] -min 1.500 [get_ports ad463x_spi_sdo]
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# relax the SDO path to help closing timing at high frequencies
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set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] 8
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set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] 7
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set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad463x_execution/inst/left_aligned_reg*] 8
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set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad463x_execution/inst/left_aligned_reg*] 7
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