219 lines
8.3 KiB
Tcl
219 lines
8.3 KiB
Tcl
###############################################################################
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## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# system level parameters
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set DEV_CONFIG $ad_project_params(DEV_CONFIG)
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set INTF $ad_project_params(INTF)
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set NUM_OF_SDI $ad_project_params(NUM_OF_SDI)
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set ADC_N_BITS [expr {$DEV_CONFIG == 2 ? 18 : 16}]
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set ADC_TO_DMA_N_BITS [expr {$ADC_N_BITS == 16 ? 16 : 32}]
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set EXT_CLK $ad_project_params(EXT_CLK)
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set TOTAL_N_BITS_DMA [expr {$ADC_TO_DMA_N_BITS*8}]
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puts "build parameters: DEV_CONFIG: $DEV_CONFIG"
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puts "build parameters: INTF: $INTF"
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puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI"
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puts "build parameters: EXT_CLK: $EXT_CLK"
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# control lines
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create_bd_port -dir I rx_busy
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create_bd_port -dir O rx_cnvst_n
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# axi_pwm_gen
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ad_ip_instance axi_pwm_gen ad7606_pwm_gen
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# dma
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ad_ip_instance axi_dmac axi_ad7606x_dma
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ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad7606x_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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switch $INTF {
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0 {
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# data, read and write lines
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create_bd_port -dir O -from 15 -to 0 rx_db_o
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create_bd_port -dir I -from 15 -to 0 rx_db_i
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create_bd_port -dir O rx_db_t
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create_bd_port -dir O rx_rd_n
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create_bd_port -dir O rx_wr_n
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# control lines
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create_bd_port -dir O rx_cs_n
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create_bd_port -dir I rx_first_data
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# instantiation
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ad_ip_instance axi_ad7606x axi_ad7606x
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ad_ip_parameter axi_ad7606x CONFIG.DEV_CONFIG $DEV_CONFIG
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ad_ip_parameter axi_ad7606x CONFIG.ADC_N_BITS $ADC_N_BITS
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ad_ip_parameter axi_ad7606x CONFIG.ADC_TO_DMA_N_BITS $ADC_TO_DMA_N_BITS
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ad_ip_parameter axi_ad7606x CONFIG.EXTERNAL_CLK $EXT_CLK
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# axi_pwm_gen
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ad_ip_parameter ad7606_pwm_gen CONFIG.ASYNC_CLK_EN 0
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ad_ip_parameter ad7606_pwm_gen CONFIG.N_PWMS 1
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if {$DEV_CONFIG == 0} {
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ad_ip_parameter ad7606_pwm_gen CONFIG.PULSE_0_WIDTH 124
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ad_ip_parameter ad7606_pwm_gen CONFIG.PULSE_0_PERIOD 125
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} else {
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ad_ip_parameter ad7606_pwm_gen CONFIG.PULSE_0_WIDTH 99
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ad_ip_parameter ad7606_pwm_gen CONFIG.PULSE_0_PERIOD 100
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}
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# dma
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ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_DATA_WIDTH_SRC $TOTAL_N_BITS_DMA
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ad_ip_instance util_cpack2 ad7606x_adc_pack
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ad_ip_parameter ad7606x_adc_pack CONFIG.NUM_OF_CHANNELS 8
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ad_ip_parameter ad7606x_adc_pack CONFIG.SAMPLE_DATA_WIDTH $ADC_TO_DMA_N_BITS
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if {$EXT_CLK == 1} {
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# use Xilinx's clocking wizard in order to generate the clock from the CPU clock, this being then assigned to the adc_clk in the axi_ad7606x IP
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ad_ip_instance clk_wiz adc_clk_generator
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ad_ip_parameter adc_clk_generator CONFIG.PRIMITIVE PLL
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ad_ip_parameter adc_clk_generator CONFIG.RESET_TYPE ACTIVE_LOW
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ad_ip_parameter adc_clk_generator CONFIG.USE_LOCKED false
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ad_ip_parameter adc_clk_generator CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 100.000
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ad_ip_parameter adc_clk_generator CONFIG.CLKOUT1_REQUESTED_PHASE 0.000
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ad_ip_parameter adc_clk_generator CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE 50.000
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ad_ip_parameter adc_clk_generator CONFIG.PRIM_SOURCE Global_buffer
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ad_ip_parameter adc_clk_generator CONFIG.CLKIN1_UI_JITTER 0
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ad_ip_parameter adc_clk_generator CONFIG.PRIM_IN_FREQ 100.000
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ad_connect sys_cpu_clk adc_clk_generator/clk_in1
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ad_connect sys_cpu_resetn adc_clk_generator/resetn
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ad_connect adc_clk_generator/clk_out1 axi_ad7606x/external_clk
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} else {
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ad_connect sys_cpu_clk axi_ad7606x/external_clk
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}
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# interface connections
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ad_connect rx_db_o axi_ad7606x/rx_db_o
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ad_connect rx_db_i axi_ad7606x/rx_db_i
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ad_connect rx_db_t axi_ad7606x/rx_db_t
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ad_connect rx_rd_n axi_ad7606x/rx_rd_n
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ad_connect rx_wr_n axi_ad7606x/rx_wr_n
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ad_connect rx_cs_n axi_ad7606x/rx_cs_n
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ad_connect rx_cnvst_n ad7606_pwm_gen/pwm_0
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ad_connect rx_busy axi_ad7606x/rx_busy
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ad_connect rx_first_data axi_ad7606x/first_data
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ad_connect sys_cpu_clk axi_ad7606x_dma/s_axi_aclk
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ad_connect sys_cpu_clk ad7606_pwm_gen/s_axi_aclk
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ad_connect sys_cpu_resetn ad7606_pwm_gen/s_axi_aresetn
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ad_connect axi_ad7606x/adc_clk ad7606x_adc_pack/clk
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ad_connect axi_ad7606x/adc_clk axi_ad7606x_dma/fifo_wr_clk
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ad_connect axi_ad7606x/adc_reset ad7606x_adc_pack/reset
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ad_connect axi_ad7606x/adc_valid ad7606x_adc_pack/fifo_wr_en
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ad_connect ad7606x_adc_pack/packed_fifo_wr axi_ad7606x_dma/fifo_wr
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ad_connect ad7606x_adc_pack/fifo_wr_overflow axi_ad7606x/adc_dovf
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for {set i 0} {$i < 8} {incr i} {
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ad_connect axi_ad7606x/adc_data_$i ad7606x_adc_pack/fifo_wr_data_$i
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ad_connect axi_ad7606x/adc_enable_$i ad7606x_adc_pack/enable_$i
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}
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# interconnect
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ad_cpu_interconnect 0x44a00000 axi_ad7606x
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ad_cpu_interconnect 0x44a30000 axi_ad7606x_dma
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ad_cpu_interconnect 0x44b00000 ad7606_pwm_gen
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# memory interconnect
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_cpu_clk axi_ad7606x_dma/m_dest_axi
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ad_connect sys_cpu_resetn axi_ad7606x_dma/m_dest_axi_aresetn
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# interrupt
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ad_cpu_interrupt ps-13 mb-12 axi_ad7606x_dma/irq
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}
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1 {
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# instantiation
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad7606_spi
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# spi engine
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
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set data_width $ADC_TO_DMA_N_BITS
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set async_spi_clk 1
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set num_cs 1
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set num_sdi $NUM_OF_SDI
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set num_sdo 1
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set sdi_delay 1
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set hier_spi_engine spi_ad7606
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spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay
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# axi_clkgen
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ad_ip_instance axi_clkgen spi_clkgen
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ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
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ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
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ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 6
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# axi_pwm_gen
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ad_ip_parameter ad7606_pwm_gen CONFIG.PULSE_0_PERIOD 120
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ad_ip_parameter ad7606_pwm_gen CONFIG.PULSE_0_WIDTH 1
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# trigger to BUSY's negative edge
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create_bd_cell -type module -reference sync_bits busy_sync
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create_bd_cell -type module -reference ad_edge_detect busy_capture
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set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture]
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ad_connect spi_clk busy_capture/clk
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ad_connect busy_capture/rst GND
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ad_connect busy_sync/out_resetn $hier_spi_engine/${hier_spi_engine}_axi_regmap/spi_resetn
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ad_connect spi_clk busy_sync/out_clk
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ad_connect busy_sync/in_bits rx_busy
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ad_connect busy_sync/out_bits busy_capture/signal_in
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ad_connect busy_capture/signal_out $hier_spi_engine/trigger
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# dma
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ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad7606x_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad7606x_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad7606x_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $data_width * $num_sdi]
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# interface connections
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ad_connect $sys_cpu_clk spi_clkgen/clk
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ad_connect $sys_cpu_clk $hier_spi_engine/clk
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ad_connect $sys_cpu_clk ad7606_pwm_gen/s_axi_aclk
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ad_connect spi_clk spi_clkgen/clk_0
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ad_connect spi_clk $hier_spi_engine/spi_clk
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ad_connect spi_clk ad7606_pwm_gen/ext_clk
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ad_connect spi_clk axi_ad7606x_dma/s_axis_aclk
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ad_connect sys_cpu_resetn ad7606_pwm_gen/s_axi_aresetn
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ad_connect sys_cpu_resetn $hier_spi_engine/resetn
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ad_connect sys_cpu_resetn axi_ad7606x_dma/m_dest_axi_aresetn
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ad_connect rx_cnvst_n ad7606_pwm_gen/pwm_0
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ad_connect axi_ad7606x_dma/s_axis $hier_spi_engine/m_axis_sample
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ad_connect ad7606_spi $hier_spi_engine/m_spi
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# interconnect
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ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
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ad_cpu_interconnect 0x44a30000 axi_ad7606x_dma
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ad_cpu_interconnect 0x44a70000 spi_clkgen
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ad_cpu_interconnect 0x44b00000 ad7606_pwm_gen
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# interrupts
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ad_cpu_interrupt ps-13 mb-13 axi_ad7606x_dma/irq
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ad_cpu_interrupt ps-12 mb-12 /$hier_spi_engine/irq
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# memory interconnect
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ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect $sys_cpu_clk axi_ad7606x_dma/m_dest_axi
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}
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}
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