371 lines
11 KiB
Verilog
371 lines
11 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input [12:0] gpio_bd_i,
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output [ 7:0] gpio_bd_o,
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inout iic_scl,
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inout iic_sda,
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input ref_clk_c_p,
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input ref_clk_c_n,
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input core_clk_c_p,
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input core_clk_c_n,
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input [ 3:0] rx_data_c_p,
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input [ 3:0] rx_data_c_n,
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output [ 3:0] tx_data_c_p,
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output [ 3:0] tx_data_c_n,
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output rx_sync_c_p,
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output rx_sync_c_n,
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output rx_os_sync_c_p,
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output rx_os_sync_c_n,
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input tx_sync_c_p,
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input tx_sync_c_n,
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input tx_sync_c_1_p,
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input tx_sync_c_1_n,
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input sysref_c_p,
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input sysref_c_n,
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inout adrv9009_tx1_enable_c,
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inout adrv9009_tx2_enable_c,
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inout adrv9009_rx1_enable_c,
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inout adrv9009_rx2_enable_c,
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inout adrv9009_reset_b_c,
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inout adrv9009_gpint_c,
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inout adrv9009_gpio_00_c,
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inout adrv9009_gpio_01_c,
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inout adrv9009_gpio_02_c,
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inout adrv9009_gpio_03_c,
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inout adrv9009_gpio_04_c,
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inout adrv9009_gpio_05_c,
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inout adrv9009_gpio_06_c,
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inout adrv9009_gpio_07_c,
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inout adrv9009_gpio_08_c,
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input ref_clk_d_p,
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input ref_clk_d_n,
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input core_clk_d_p,
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input core_clk_d_n,
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input [ 3:0] rx_data_d_p,
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input [ 3:0] rx_data_d_n,
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output [ 3:0] tx_data_d_p,
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output [ 3:0] tx_data_d_n,
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output rx_sync_d_p,
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output rx_sync_d_n,
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output rx_os_sync_d_p,
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output rx_os_sync_d_n,
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input tx_sync_d_p,
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input tx_sync_d_n,
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input tx_sync_d_1_p,
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input tx_sync_d_1_n,
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input sysref_d_p,
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input sysref_d_n,
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inout adrv9009_tx1_enable_d,
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inout adrv9009_tx2_enable_d,
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inout adrv9009_rx1_enable_d,
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inout adrv9009_rx2_enable_d,
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inout adrv9009_reset_b_d,
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inout adrv9009_gpint_d,
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inout adrv9009_gpio_00_d,
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inout adrv9009_gpio_01_d,
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inout adrv9009_gpio_02_d,
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inout adrv9009_gpio_03_d,
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inout adrv9009_gpio_04_d,
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inout adrv9009_gpio_05_d,
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inout adrv9009_gpio_06_d,
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inout adrv9009_gpio_07_d,
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inout adrv9009_gpio_08_d,
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input fan_tach,
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input fan_pwm,
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output hmc7044_reset,
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inout hmc7044_sync,
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inout hmc7044_gpio_1,
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inout hmc7044_gpio_2,
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inout hmc7044_gpio_3,
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inout hmc7044_gpio_4,
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output spi_csn_hmc7044,
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output spi_csn_adrv9009_c,
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output spi_csn_adrv9009_d,
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output spi_clk,
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inout spi_sdio,
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input spi_miso
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);
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// internal signals
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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wire [94:0] gpio_t;
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wire [20:0] gpio_bd;
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wire [2:0] spi_csn;
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wire ref_clk_c;
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wire core_clk_c;
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wire core_clk_c_ds;
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wire rx_sync_rx;
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wire tx_sync_c;
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wire sysref_c;
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wire ref_clk_d;
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wire core_clk_d;
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wire core_clk_d_ds;
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wire rx_sync_obs;
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wire rx_os_sync_d;
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wire tx_sync_d;
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wire sysref_d;
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wire tx_sync;
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wire spi_mosi;
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wire spi0_miso;
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// The csn bus from the SPI controller needs to be decoded as
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// is-decoded-cs = <1> is set in the device tree.
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reg [7:0] spi_3_to_8_csn;
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always @(*) begin
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case (spi_csn)
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3'h0: spi_3_to_8_csn = 8'b11111110;
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3'h1: spi_3_to_8_csn = 8'b11111101;
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3'h2: spi_3_to_8_csn = 8'b11111011;
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default: spi_3_to_8_csn = 8'b11111111;
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endcase
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end
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assign spi_csn_adrv9009_c = spi_3_to_8_csn[0];
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assign spi_csn_adrv9009_d = spi_3_to_8_csn[1];
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assign spi_csn_hmc7044 = spi_3_to_8_csn[2];
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fmcomms8_spi i_spi (
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.spi_csn(spi_3_to_8_csn),
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.spi_clk(spi_clk),
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.spi_mosi(spi_mosi),
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.spi_miso_i(spi_miso),
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.spi_miso_o(spi0_miso),
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.spi_sdio(spi_sdio));
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assign tx_sync = tx_sync_c & tx_sync_d;
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assign gpio_i[94:68] = gpio_o[94:68];
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assign gpio_i[31:21] = gpio_o[31:21];
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assign gpio_i[ 7: 0] = gpio_o[ 7: 0];
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assign gpio_i[20: 8] = gpio_bd_i;
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assign gpio_bd_o = gpio_o[ 7: 0];
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// instantiations
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ad_iobuf #(
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.DATA_WIDTH(36)
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) i_iobuf (
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.dio_t ({gpio_t[67:32]}),
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.dio_i ({gpio_o[67:32]}),
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.dio_o ({gpio_i[67:32]}),
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.dio_p ({
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hmc7044_gpio_4, // 67
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hmc7044_gpio_3, // 66
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hmc7044_gpio_2, // 65
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hmc7044_gpio_1, // 64
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hmc7044_sync, // 63
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hmc7044_reset, // 62
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adrv9009_tx2_enable_d, // 61
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adrv9009_tx1_enable_d, // 60
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adrv9009_rx2_enable_d, // 59
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adrv9009_rx1_enable_d, // 58
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adrv9009_reset_b_d, // 57
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adrv9009_gpint_d, // 56
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adrv9009_gpio_08_d, // 55
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adrv9009_gpio_07_d, // 54
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adrv9009_gpio_06_d, // 53
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adrv9009_gpio_05_d, // 52
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adrv9009_gpio_04_d, // 51
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adrv9009_gpio_03_d, // 50
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adrv9009_gpio_02_d, // 49
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adrv9009_gpio_01_d, // 48
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adrv9009_gpio_00_d, // 47
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adrv9009_tx2_enable_c, // 46
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adrv9009_tx1_enable_c, // 45
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adrv9009_rx2_enable_c, // 44
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adrv9009_rx1_enable_c, // 43
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adrv9009_reset_b_c, // 42
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adrv9009_gpint_c, // 41
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adrv9009_gpio_08_c, // 40
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adrv9009_gpio_07_c, // 39
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adrv9009_gpio_06_c, // 38
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adrv9009_gpio_05_c, // 37
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adrv9009_gpio_04_c, // 36
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adrv9009_gpio_03_c, // 35
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adrv9009_gpio_02_c, // 34
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adrv9009_gpio_01_c, // 33
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adrv9009_gpio_00_c})); // 32
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IBUFDS_GTE4 i_ibufds_ref_clk_1 (
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.CEB (1'd0),
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.I (ref_clk_c_p),
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.IB (ref_clk_c_n),
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.O (ref_clk_c),
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.ODIV2 ());
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IBUFDS_GTE4 i_ibufds_ref_clk_2 (
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.CEB (1'd0),
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.I (ref_clk_d_p),
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.IB (ref_clk_d_n),
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.O (ref_clk_d),
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.ODIV2 ());
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IBUFDS i_ibufds_sysref_1 (
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.I (sysref_c_p),
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.IB (sysref_c_n),
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.O (sysref_c));
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IBUFDS i_ibufds_sysref_2 (
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.I (sysref_d_p),
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.IB (sysref_d_n),
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.O (sysref_d));
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IBUFDS i_rx_clk_ibuf_1 (
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.I (core_clk_c_p),
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.IB (core_clk_c_n),
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.O (core_clk_c_ds));
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BUFG i_rx_clk_ibufg_1 (
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.I (core_clk_c_ds),
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.O (core_clk_c));
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IBUFDS i_rx_clk_ibuf_2 (
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.I (core_clk_d_p),
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.IB (core_clk_d_n),
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.O (core_clk_d_ds));
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BUFG i_rx_clk_ibufg_2(
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.I (core_clk_d_ds),
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.O (core_clk_d));
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IBUFDS i_ibufds_tx_sync_1 (
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.I (tx_sync_c_p),
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.IB (tx_sync_c_n),
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.O (tx_sync_c));
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IBUFDS i_ibufds_tx_sync_2 (
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.I (tx_sync_d_p),
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.IB (tx_sync_d_n),
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.O (tx_sync_d));
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OBUFDS i_obufds_rx_sync_1 (
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.I (rx_sync_rx),
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.O (rx_sync_c_p),
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.OB (rx_sync_c_n));
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OBUFDS i_obufds_rx_os_sync_1 (
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.I (rx_sync_obs),
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.O (rx_os_sync_c_p),
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.OB (rx_os_sync_c_n));
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OBUFDS i_obufds_rx_sync_2 (
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.I (rx_sync_rx),
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.O (rx_sync_d_p),
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.OB (rx_sync_d_n));
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OBUFDS i_obufds_rx_os_sync_2 (
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.I (rx_sync_obs),
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.O (rx_os_sync_d_p),
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.OB (rx_os_sync_d_n));
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system_wrapper i_system_wrapper (
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.core_clk_c(core_clk_c),
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.core_clk_d(core_clk_d),
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.ref_clk_c(ref_clk_c),
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.ref_clk_d(ref_clk_d),
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.rx_data_0_n (rx_data_c_n[0]),
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.rx_data_0_p (rx_data_c_p[0]),
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.rx_data_1_n (rx_data_c_n[1]),
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.rx_data_1_p (rx_data_c_p[1]),
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.rx_data_2_n (rx_data_c_n[2]),
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.rx_data_2_p (rx_data_c_p[2]),
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.rx_data_3_n (rx_data_c_n[3]),
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.rx_data_3_p (rx_data_c_p[3]),
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.rx_data_4_n (rx_data_d_n[0]),
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.rx_data_4_p (rx_data_d_p[0]),
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.rx_data_5_n (rx_data_d_n[1]),
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.rx_data_5_p (rx_data_d_p[1]),
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.rx_data_6_n (rx_data_d_n[2]),
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.rx_data_6_p (rx_data_d_p[2]),
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.rx_data_7_n (rx_data_d_n[3]),
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.rx_data_7_p (rx_data_d_p[3]),
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.rx_sync_0 (rx_sync_rx),
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.rx_sync_4 (rx_sync_obs),
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.rx_sysref_0 (sysref_d),
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.rx_sysref_4 (sysref_c),
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.tx_data_0_n (tx_data_c_n[0]),
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.tx_data_0_p (tx_data_c_p[0]),
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.tx_data_1_n (tx_data_c_n[1]),
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.tx_data_1_p (tx_data_c_p[1]),
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.tx_data_2_n (tx_data_c_n[2]),
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.tx_data_2_p (tx_data_c_p[2]),
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.tx_data_3_n (tx_data_c_n[3]),
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.tx_data_3_p (tx_data_c_p[3]),
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.tx_data_4_n (tx_data_d_n[0]),
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.tx_data_4_p (tx_data_d_p[0]),
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.tx_data_5_n (tx_data_d_n[1]),
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.tx_data_5_p (tx_data_d_p[1]),
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.tx_data_6_n (tx_data_d_n[2]),
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.tx_data_6_p (tx_data_d_p[2]),
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.tx_data_7_n (tx_data_d_n[3]),
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.tx_data_7_p (tx_data_d_p[3]),
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.tx_sync_0 (tx_sync),
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.tx_sysref_0 (sysref_c),
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.dac_fifo_bypass(gpio_o[68]),
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.spi0_sclk (spi_clk),
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.spi0_csn (spi_csn),
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.spi0_miso (spi0_miso),
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.spi0_mosi (spi_mosi),
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.spi1_sclk (),
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.spi1_csn (),
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.spi1_miso (1'b0),
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.spi1_mosi ());
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endmodule
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