176 lines
9.6 KiB
Tcl
176 lines
9.6 KiB
Tcl
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# fmcomms2
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create_bd_port -dir I rx_clk_in_p
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create_bd_port -dir I rx_clk_in_n
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create_bd_port -dir I rx_frame_in_p
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create_bd_port -dir I rx_frame_in_n
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create_bd_port -dir I -from 5 -to 0 rx_data_in_p
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create_bd_port -dir I -from 5 -to 0 rx_data_in_n
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create_bd_port -dir O tx_clk_out_p
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create_bd_port -dir O tx_clk_out_n
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create_bd_port -dir O tx_frame_out_p
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create_bd_port -dir O tx_frame_out_n
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create_bd_port -dir O -from 5 -to 0 tx_data_out_p
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create_bd_port -dir O -from 5 -to 0 tx_data_out_n
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create_bd_port -dir O enable
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create_bd_port -dir O txnrx
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# ad9361 core
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set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
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set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9361
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set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma
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set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack]
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set_property -dict [list CONFIG.CH_CNT {4}] $util_ad9361_dac_upack
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set_property -dict [list CONFIG.CH_DW {16}] $util_ad9361_dac_upack
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set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma
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set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack]
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set_property -dict [list CONFIG.CH_CNT {4}] $util_ad9361_adc_pack
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set_property -dict [list CONFIG.CH_DW {16}] $util_ad9361_adc_pack
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set util_ad9361_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9361_adc_fifo]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_fifo
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set_property -dict [list CONFIG.DIN_ADDR_WIDTH {4}] $util_ad9361_adc_fifo
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set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo
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set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
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# connections
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ad_connect sys_200m_clk axi_ad9361/delay_clk
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ad_connect axi_ad9361_clk axi_ad9361/l_clk
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ad_connect axi_ad9361_clk axi_ad9361/clk
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ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p
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ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n
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ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p
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ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n
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ad_connect rx_data_in_p axi_ad9361/rx_data_in_p
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ad_connect rx_data_in_n axi_ad9361/rx_data_in_n
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ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p
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ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n
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ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p
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ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n
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ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
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ad_connect tx_data_out_n axi_ad9361/tx_data_out_n
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ad_connect enable axi_ad9361/enable
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ad_connect txnrx axi_ad9361/txnrx
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ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk
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ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
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ad_connect sys_cpu_clk util_ad9361_adc_fifo/dout_clk
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ad_connect sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn
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ad_connect sys_cpu_clk util_ad9361_adc_pack/adc_clk
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ad_connect sys_cpu_reset util_ad9361_adc_pack/adc_rst
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ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk
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ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
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ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
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ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
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ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1
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ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1
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ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1
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ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2
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ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2
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ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2
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ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3
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ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3
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ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3
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ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0
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ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0
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ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0
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ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1
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ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1
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ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1
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ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2
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ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2
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ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2
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ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3
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ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3
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ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3
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ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
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ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
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ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
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ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
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ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
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ad_connect axi_ad9361_clk util_ad9361_dac_upack/dac_clk
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ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
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ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0
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ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0
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ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
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ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
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ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
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ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
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ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
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ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
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ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
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ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
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ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
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ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
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ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
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ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
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ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
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# interconnects
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ad_cpu_interconnect 0x79020000 axi_ad9361
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ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
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ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
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ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
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ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
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# interrupts
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ad_cpu_interrupt ps-13 mb-12 axi_ad9361_adc_dma/irq
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ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq
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# ila (adc)
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set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_adc]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
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set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
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set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE4_WIDTH {1}] $ila_adc
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ad_connect util_ad9361_adc_fifo/dout_data_0 ila_adc/probe0
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ad_connect util_ad9361_adc_fifo/dout_data_1 ila_adc/probe1
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ad_connect util_ad9361_adc_fifo/dout_data_2 ila_adc/probe2
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ad_connect util_ad9361_adc_fifo/dout_data_3 ila_adc/probe3
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ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_adc/probe4
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ad_connect sys_cpu_clk ila_adc/clk
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