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altera
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avl_dacfifo: Fix avl_address generation
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2017-12-15 12:17:47 +00:00 |
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axi_ad5766
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad6676
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad7616
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axi_ad7616: Add missing port to instantiation
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2018-04-11 15:09:54 +03:00 |
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axi_ad9122
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad9144
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avl_adxcvr: Perform octet order swap
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2017-08-03 17:57:58 +02:00 |
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axi_ad9152
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad9162
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad9250
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Remove unused Q_OR_I_N parameter from JESD204 ADC cores
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2018-02-20 16:33:16 +01:00 |
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axi_ad9265
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad9361
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad9371
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad9379
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad9434
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axi_ad9434: Make adc_enable controllable from the channel register map
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2018-04-11 15:09:54 +03:00 |
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axi_ad9467
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad9625
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad9671
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axi_ad9671: Fix typo
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2017-08-07 10:54:45 +01:00 |
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axi_ad9680
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad9684
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad9739a
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axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
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2018-04-11 15:09:54 +03:00 |
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axi_ad9963
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axi_ad9963: Fix port dependency definition
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2018-04-11 15:09:54 +03:00 |
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axi_adc_decimate
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constraints: up_xfer_cntrl and up_xfer_status have its own constraints
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2018-04-11 15:09:54 +03:00 |
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axi_adc_trigger
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constraints: up_xfer_cntrl and up_xfer_status have its own constraints
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2018-04-11 15:09:54 +03:00 |
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axi_clkgen
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axi_clkgen: add ultrascale series support
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2018-02-13 17:33:38 +02:00 |
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axi_dac_interpolate
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constraints: up_xfer_cntrl and up_xfer_status have its own constraints
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2018-04-11 15:09:54 +03:00 |
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axi_dmac
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axi_dmac: In SDP mode REGCEB is connected to GND
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2018-04-11 15:09:54 +03:00 |
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axi_fmcadc5_sync
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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axi_generic_adc
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library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
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2017-08-01 15:21:25 +02:00 |
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axi_gpreg
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library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
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2017-08-01 15:21:25 +02:00 |
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axi_hdmi_rx
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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axi_hdmi_tx
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axi_hdmi_tx: Updated .sdc constraints
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2018-04-11 15:09:54 +03:00 |
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axi_i2s_adi
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library: Update
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2017-11-15 17:08:45 +02:00 |
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axi_intr_monitor
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library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
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2017-08-01 15:21:25 +02:00 |
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axi_logic_analyzer
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constraints: up_xfer_cntrl and up_xfer_status have its own constraints
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2018-04-11 15:09:54 +03:00 |
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axi_mc_controller
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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axi_mc_current_monitor
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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axi_mc_speed
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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axi_rd_wr_combiner
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license: Add some clarification to the header license
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2017-05-31 18:18:56 +03:00 |
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axi_spdif_rx
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license: Add some clarification to the header license
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2017-05-31 18:18:56 +03:00 |
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axi_spdif_tx
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license: Add some clarification to the header license
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2017-05-31 18:18:56 +03:00 |
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axi_usb_fx3
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library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
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2017-08-01 15:21:25 +02:00 |
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cn0363
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license: Add some clarification to the header license
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2017-05-31 18:18:56 +03:00 |
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common
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axi_hdmi_tx: Use abstract multiplier module supporting both Xilinx and Intel FPGAs
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2018-04-11 15:09:54 +03:00 |
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cordic_demod
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license: Add some clarification to the header license
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2017-05-31 18:18:56 +03:00 |
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interfaces
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interface: Update the transceiver interfaces
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2017-09-25 18:02:04 +01:00 |
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jesd204
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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prcfg
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license: Add some clarification to the header license
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2017-05-31 18:18:56 +03:00 |
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scripts
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scripts:adi_ip: Update web address format
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2018-04-11 15:09:54 +03:00 |
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spi_engine
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spi_engine:axi_spi_engine: Add missing port to instantiations
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2018-04-11 15:09:54 +03:00 |
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util_adcfifo
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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util_axis_fifo
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Make: Use $(MAKE) for recursive make commands
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2018-03-07 07:40:19 +00:00 |
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util_axis_resize
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util_axis_resize: Coding style updates
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2017-08-07 11:23:57 +03:00 |
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util_axis_upscale
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util_axis_upscale: Initial commit
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2018-04-11 15:09:54 +03:00 |
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util_bsplit
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Remove executable flag from non-executable files
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2017-07-28 17:56:07 +02:00 |
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util_cdc
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util_cdc: Add helper function for creating constraints for the CDC blocks
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2017-08-21 11:05:16 +02:00 |
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util_cic
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jesd204-sub-ip- no top files
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2017-06-01 15:48:48 -04:00 |
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util_clkdiv
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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util_cpack
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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util_dacfifo
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Make: Update makefiles
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2017-11-20 14:27:39 +02:00 |
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util_delay
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util_delay: Initial commit
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2017-05-25 15:12:10 +03:00 |
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util_extract
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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util_fir_dec
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license: Add some clarification to the header license
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2017-05-31 18:18:56 +03:00 |
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util_fir_int
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util_fir_int: Fix valid assignment
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2017-06-06 17:53:41 +03:00 |
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util_gmii_to_rgmii
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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util_i2c_mixer
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license: Add some clarification to the header license
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2017-05-31 18:18:56 +03:00 |
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util_mfifo
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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util_pulse_gen
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util_pulse_gen: Add Makefile
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2017-04-27 11:28:25 +03:00 |
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util_rfifo
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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util_sigma_delta_spi
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license: Add some clarification to the header license
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2017-05-31 18:18:56 +03:00 |
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util_tdd_sync
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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util_upack
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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util_var_fifo
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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util_wfifo
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axi_*: Infer clock and reset signals of an IP
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2018-04-11 15:09:54 +03:00 |
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xilinx
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axi_dacfifo: Rewrote constraints to be more specific
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2018-04-11 15:09:54 +03:00 |
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Makefile
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util_axis_upscale: Initial commit
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2018-04-11 15:09:54 +03:00 |
25ffb91dc6