277161c143
We need to make sure to not prematurely de-assert the s_valid signal for the request splitter when disabling the DMAC. Otherwise it is possible that under certain conditions the DMAC is disabled with a partially accepted request and when it is enabled again it will continue in an inconsistent state which can lead to transfer corruption or pipeline stalls. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
||
---|---|---|
library | ||
projects | ||
.gitignore | ||
LICENSE | ||
README.md |
README.md
hdl
Analog Devices HDL libraries and projects
Tools version:
- Vivado 2014.2
- Quartus 14.0
First time users, it is highly recommended to go through our HDL user guide at the following url:
http://wiki.analog.com/resources/fpga/docs/hdl
For support please visit our FPGA Reference Designs Support Community on EngineerZone: