27b786e92f
Since we are just doing a loopback all the logic is contained within the IO bank. By using a BUFIO instead of a BUFG we avoid having to route the clock signal from the IO bank to the middle of the FPGA and back to the IO bank. This reduces the skew between clock and the data signals and makes sure that the we can use the same design over a range of different resolutions without having to calibrate the delay. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
hdl
Analog Devices HDL libraries and projects
Tools version:
- Vivado 2014.4.1
- Quartus 14.0
First time users, it is highly recommended to go through our HDL user guide at the following url:
http://wiki.analog.com/resources/fpga/docs/hdl
For support please visit our FPGA Reference Designs Support Community on EngineerZone: