217 lines
7.2 KiB
Verilog
217 lines
7.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9671_if #(
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parameter QUAD_OR_DUAL_N = 1,
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parameter ID = 0
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) (
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// jesd interface
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// rx_clk is (line-rate/40)
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input rx_clk,
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input [ 3:0] rx_sof,
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input [(64*QUAD_OR_DUAL_N)+63:0] rx_data,
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// adc data output
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output adc_clk,
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input adc_rst,
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output adc_valid,
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output reg [ 15:0] adc_data_a,
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output adc_or_a,
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output reg [ 15:0] adc_data_b,
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output adc_or_b,
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output reg [ 15:0] adc_data_c,
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output adc_or_c,
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output reg [ 15:0] adc_data_d,
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output adc_or_d,
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output reg [ 15:0] adc_data_e,
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output adc_or_e,
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output reg [ 15:0] adc_data_f,
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output adc_or_f,
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output reg [ 15:0] adc_data_g,
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output adc_or_g,
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output reg [ 15:0] adc_data_h,
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output adc_or_h,
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input [ 31:0] adc_start_code,
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input adc_sync_in,
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output adc_sync_out,
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input adc_sync,
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output reg adc_sync_status,
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output reg adc_status,
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input [ 3:0] adc_raddr_in,
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output reg [ 3:0] adc_raddr_out
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);
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// internal wires
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wire [(2*QUAD_OR_DUAL_N)+1:0] rx_sof_s;
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wire [(64*QUAD_OR_DUAL_N)+63:0] rx_data_s;
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wire [127:0] adc_wdata;
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wire [127:0] adc_rdata;
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wire [ 15:0] adc_data_a_s;
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wire [ 15:0] adc_data_b_s;
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wire [ 15:0] adc_data_c_s;
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wire [ 15:0] adc_data_d_s;
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wire [ 15:0] adc_data_e_s;
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wire [ 15:0] adc_data_f_s;
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wire [ 15:0] adc_data_g_s;
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wire [ 15:0] adc_data_h_s;
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wire [ 3:0] adc_raddr_s;
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wire adc_sync_s;
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// internal registers
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reg int_valid = 'd0;
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reg [127:0] int_data = 'd0;
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reg rx_sof_d = 'd0;
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reg [ 3:0] adc_waddr = 'd0;
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// adc clock & valid
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assign adc_clk = rx_clk;
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assign adc_valid = int_valid;
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assign adc_sync_out = adc_sync;
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assign adc_or_a = 'd0;
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assign adc_or_b = 'd0;
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assign adc_or_c = 'd0;
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assign adc_or_d = 'd0;
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assign adc_or_e = 'd0;
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assign adc_or_f = 'd0;
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assign adc_or_g = 'd0;
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assign adc_or_h = 'd0;
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assign adc_data_a_s = {int_data[ 7: 0], int_data[ 15: 8]};
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assign adc_data_b_s = {int_data[ 23: 16], int_data[ 31: 24]};
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assign adc_data_c_s = {int_data[ 39: 32], int_data[ 47: 40]};
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assign adc_data_d_s = {int_data[ 55: 48], int_data[ 63: 56]};
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assign adc_data_e_s = {int_data[ 71: 64], int_data[ 79: 72]};
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assign adc_data_f_s = {int_data[ 87: 80], int_data[ 95: 88]};
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assign adc_data_g_s = {int_data[103: 96], int_data[111:104]};
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assign adc_data_h_s = {int_data[119:112], int_data[127:120]};
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assign adc_wdata = {adc_data_h_s, adc_data_g_s, adc_data_f_s, adc_data_e_s,
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adc_data_d_s, adc_data_c_s, adc_data_b_s, adc_data_a_s};
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assign adc_raddr_s = (ID == 0) ? adc_raddr_out : adc_raddr_in;
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assign adc_sync_s = (ID == 0) ? adc_sync_out : adc_sync_in;
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always @(posedge rx_clk) begin
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adc_data_a <= adc_rdata[ 15: 0];
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adc_data_b <= adc_rdata[ 31: 16];
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adc_data_c <= adc_rdata[ 47: 32];
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adc_data_d <= adc_rdata[ 63: 48];
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adc_data_e <= adc_rdata[ 79: 64];
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adc_data_f <= adc_rdata[ 95: 80];
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adc_data_g <= adc_rdata[111: 96];
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adc_data_h <= adc_rdata[127:112];
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end
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always @(posedge rx_clk) begin
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if (adc_rst == 1'b1) begin
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adc_waddr <= 4'h0;
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adc_raddr_out <= 4'h8;
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adc_sync_status <= 1'b0;
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end else begin
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if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
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adc_sync_status <= 1'b0;
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end else if(adc_sync_s == 1'b1) begin
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adc_sync_status <= 1'b1;
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end
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if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
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adc_waddr <= 4'h0;
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adc_raddr_out <= 4'h8;
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end else if (int_valid == 1'b1) begin
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adc_waddr <= adc_waddr + 1;
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adc_raddr_out <= adc_raddr_out + 1;
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end
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end
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end
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always @(posedge rx_clk) begin
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if (QUAD_OR_DUAL_N == 1'b1) begin
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int_valid <= 1'b1;
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int_data <= rx_data_s;
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end else begin
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rx_sof_d <= &rx_sof_s;
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int_valid <= rx_sof_d;
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int_data[63:0] <= {rx_data_s[31: 0], int_data[ 63:32]};
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int_data[127:64] <= {rx_data_s[63:32], int_data[127:96]};
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end
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end
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always @(posedge rx_clk) begin
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if (adc_rst == 1'b1) begin
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adc_status <= 1'b0;
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end else begin
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adc_status <= 1'b1;
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end
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end
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ad_mem #(
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.ADDRESS_WIDTH(4),
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.DATA_WIDTH(128)
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) i_mem (
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.clka(rx_clk),
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.wea(int_valid),
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.addra(adc_waddr),
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.dina(adc_wdata),
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.clkb(rx_clk),
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.reb (1'b1),
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.addrb(adc_raddr_s),
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.doutb(adc_rdata));
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// frame-alignment
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genvar n;
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generate
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for (n = 0; n < ((2*QUAD_OR_DUAL_N)+2); n = n + 1) begin: g_xcvr_if
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ad_xcvr_rx_if i_xcvr_if (
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.rx_clk (rx_clk),
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.rx_ip_sof (rx_sof),
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.rx_ip_data (rx_data[((n*32)+31):(n*32)]),
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.rx_sof (rx_sof_s[n]),
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.rx_data (rx_data_s[((n*32)+31):(n*32)]));
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end
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endgenerate
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endmodule
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