181 lines
6.2 KiB
Verilog
181 lines
6.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// PN monitors
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`timescale 1ns/100ps
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module axi_ad9671_pnmon (
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// adc interface
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input adc_clk,
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input adc_valid,
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input [15:0] adc_data,
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// pn out of sync and error
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output adc_pn_oos,
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output adc_pn_err,
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input [ 3:0] adc_pnseq_sel
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);
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// internal registers
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reg adc_pn_valid = 'd0;
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reg [31:0] adc_pn_data_in = 'd0;
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reg [31:0] adc_pn_data_pn = 'd0;
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// internal signals
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wire adc_pn_valid_s;
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wire [31:0] adc_pn_data_pn_s;
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// PN23 function
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function [31:0] pn23;
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input [31:0] din;
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reg [31:0] dout;
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begin
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dout[31] = din[22] ^ din[17];
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dout[30] = din[21] ^ din[16];
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dout[29] = din[20] ^ din[15];
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dout[28] = din[19] ^ din[14];
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dout[27] = din[18] ^ din[13];
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dout[26] = din[17] ^ din[12];
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dout[25] = din[16] ^ din[11];
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dout[24] = din[15] ^ din[10];
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dout[23] = din[14] ^ din[ 9];
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dout[22] = din[13] ^ din[ 8];
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dout[21] = din[12] ^ din[ 7];
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dout[20] = din[11] ^ din[ 6];
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dout[19] = din[10] ^ din[ 5];
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dout[18] = din[ 9] ^ din[ 4];
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dout[17] = din[ 8] ^ din[ 3];
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dout[16] = din[ 7] ^ din[ 2];
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dout[15] = din[ 6] ^ din[ 1];
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dout[14] = din[ 5] ^ din[ 0];
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dout[13] = din[ 4] ^ din[22] ^ din[17];
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dout[12] = din[ 3] ^ din[21] ^ din[16];
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dout[11] = din[ 2] ^ din[20] ^ din[15];
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dout[10] = din[ 1] ^ din[19] ^ din[14];
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dout[ 9] = din[ 0] ^ din[18] ^ din[13];
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dout[ 8] = din[22] ^ din[12];
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dout[ 7] = din[21] ^ din[11];
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dout[ 6] = din[20] ^ din[10];
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dout[ 5] = din[19] ^ din[ 9];
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dout[ 4] = din[18] ^ din[ 8];
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dout[ 3] = din[17] ^ din[ 7];
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dout[ 2] = din[16] ^ din[ 6];
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dout[ 1] = din[15] ^ din[ 5];
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dout[ 0] = din[14] ^ din[ 4];
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pn23 = dout;
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end
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endfunction
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// PN9 function
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function [31:0] pn9;
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input [31:0] din;
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reg [31:0] dout;
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begin
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dout[31] = din[ 8] ^ din[ 4];
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dout[30] = din[ 7] ^ din[ 3];
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dout[29] = din[ 6] ^ din[ 2];
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dout[28] = din[ 5] ^ din[ 1];
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dout[27] = din[ 4] ^ din[ 0];
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dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
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dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
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dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
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dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
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dout[22] = din[ 8] ^ din[ 0];
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dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
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dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
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dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
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dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
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dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
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dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
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dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
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dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
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dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
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dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
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dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
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dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
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dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
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dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
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dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
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dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
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dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
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dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
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dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
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dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
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dout[ 1] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
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dout[ 0] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
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pn9 = dout;
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end
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endfunction
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// pn sequence select
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assign adc_pn_valid_s = adc_valid & adc_pn_valid;
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assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
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always @(posedge adc_clk) begin
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if (adc_valid == 1'b1) begin
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adc_pn_valid <= ~adc_pn_valid;
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adc_pn_data_in <= {adc_pn_data_in[15:0], ~adc_data[15], adc_data[14:0]};
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end
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if (adc_pn_valid_s == 1'b1) begin
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if (adc_pnseq_sel == 4'd0) begin
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adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
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end else begin
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adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
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end
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end
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end
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// pn oos & pn err
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ad_pnmon #(
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.DATA_WIDTH(32)
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) i_pnmon (
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.adc_clk (adc_clk),
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.adc_valid_in (adc_pn_valid_s),
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.adc_data_in (adc_pn_data_in),
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.adc_data_pn (adc_pn_data_pn),
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.adc_pn_oos (adc_pn_oos),
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.adc_pn_err (adc_pn_err));
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endmodule
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