342 lines
9.9 KiB
Verilog
342 lines
9.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9434_if (
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// device interface
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adc_clk_in_p,
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adc_clk_in_n,
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adc_data_in_p,
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adc_data_in_n,
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adc_or_in_p,
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adc_or_in_n,
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// interface outputs
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adc_data_s0,
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adc_or_s0,
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adc_data_s1,
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adc_or_s1,
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adc_data_s2,
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adc_or_s2,
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adc_data_s3,
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adc_or_s3,
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// internl reset and clocks
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adc_clk,
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adc_rst,
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adc_status,
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// delay interface (for IDELAY macros)
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delay_clk,
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delay_rst,
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delay_sel,
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delay_rwn,
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delay_addr,
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delay_wdata,
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delay_rdata,
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delay_ack_t,
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delay_locked,
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// mmcm reset
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mmcm_rst,
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// drp interface for MMCM
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drp_clk,
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drp_rst,
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drp_sel,
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drp_wr,
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drp_addr,
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drp_wdata,
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drp_rdata,
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drp_ready,
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drp_locked);
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// parameters
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parameter PCORE_DEVTYPE = 0; // 0 - 7Series / 1 - 6Series
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parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
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// buffer type based on the target device.
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localparam PCORE_BUFTYPE = PCORE_DEVTYPE;
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// adc interface (clk, data, over-range)
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input adc_clk_in_p;
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input adc_clk_in_n;
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input [11:0] adc_data_in_p;
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input [11:0] adc_data_in_n;
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input adc_or_in_p;
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input adc_or_in_n;
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// interface outputs
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output [11:0] adc_data_s0;
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output adc_or_s0;
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output [11:0] adc_data_s1;
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output adc_or_s1;
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output [11:0] adc_data_s2;
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output adc_or_s2;
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output [11:0] adc_data_s3;
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output adc_or_s3;
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// internal reset and clocks
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output adc_clk;
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input adc_rst;
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output adc_status;
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// delay control signals
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input delay_clk;
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input delay_rst;
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input delay_sel;
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input delay_rwn;
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input [ 7:0] delay_addr;
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input [ 4:0] delay_wdata;
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output [ 4:0] delay_rdata;
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output delay_ack_t;
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output delay_locked;
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// mmcm reset
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input mmcm_rst;
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// drp interface
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input drp_clk;
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input drp_rst;
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input drp_sel;
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input drp_wr;
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input [11:0] drp_addr;
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input [15:0] drp_wdata;
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output [15:0] drp_rdata;
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output drp_ready;
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output drp_locked;
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// output registers
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reg [ 4:0] delay_rdata = 'b0;
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reg delay_ack_t = 'b0;
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reg [47:0] adc_data = 'b0;
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reg adc_or = 'b0;
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// internal registers
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reg [12:0] delay_ld = 'd0;
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reg adc_status = 'd0;
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reg adc_status_m1 = 'd0;
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// internal signals
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wire [11:0] adc_data_p_s;
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wire [11:0] adc_data_n_s;
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wire adc_or_p_s;
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wire adc_or_n_s;
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wire [ 4:0] delay_rdata_s[12:0];
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wire adc_clk_in;
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wire adc_div_clk;
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genvar l_inst;
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// output assignment for adc clock (1:4 of the sampling clock)
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assign adc_clk = adc_div_clk;
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// delay write interface, each delay element can be individually
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// addressed, and a delay value can be directly loaded (no inc/dec stuff)
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always @(posedge delay_clk) begin
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if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
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case (delay_addr)
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8'd12 : delay_ld <= 13'h1000;
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8'd11 : delay_ld <= 13'h0800;
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8'd10 : delay_ld <= 13'h0400;
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8'd9 : delay_ld <= 13'h0200;
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8'd8 : delay_ld <= 13'h0100;
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8'd7 : delay_ld <= 13'h0080;
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8'd6 : delay_ld <= 13'h0040;
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8'd5 : delay_ld <= 13'h0020;
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8'd4 : delay_ld <= 13'h0010;
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8'd3 : delay_ld <= 13'h0008;
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8'd2 : delay_ld <= 13'h0004;
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8'd1 : delay_ld <= 13'h0002;
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8'd0 : delay_ld <= 13'h0001;
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default : delay_ld <= 13'h0000;
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endcase
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end else begin
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delay_ld <= 13'h000;
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end
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end
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// delay read interface, a delay ack toggle is used to transfer data to the
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// processor side- delay locked is independently transferred
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always @(posedge delay_clk) begin
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case (delay_addr)
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8'd12 : delay_rdata <= delay_rdata_s[12];
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8'd11 : delay_rdata <= delay_rdata_s[11];
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8'd10 : delay_rdata <= delay_rdata_s[10];
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8'd9 : delay_rdata <= delay_rdata_s[9];
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8'd8 : delay_rdata <= delay_rdata_s[8];
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8'd7 : delay_rdata <= delay_rdata_s[7];
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8'd6 : delay_rdata <= delay_rdata_s[6];
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8'd5 : delay_rdata <= delay_rdata_s[5];
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8'd4 : delay_rdata <= delay_rdata_s[4];
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8'd3 : delay_rdata <= delay_rdata_s[3];
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8'd2 : delay_rdata <= delay_rdata_s[2];
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8'd1 : delay_rdata <= delay_rdata_s[1];
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8'd0 : delay_rdata <= delay_rdata_s[0];
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default: delay_rdata <= 5'd0;
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endcase
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if (delay_sel == 1'b1) begin
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delay_ack_t <= ~delay_ack_t;
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end
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end
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// data interface
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generate
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for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin : g_adc_if
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ad_lvds_in #(
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.BUFTYPE (PCORE_BUFTYPE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (PCORE_IODELAY_GROUP))
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i_adc_data (
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.rx_clk (adc_clk_in),
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.rx_data_in_p (adc_data_in_p[l_inst]),
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.rx_data_in_n (adc_data_in_n[l_inst]),
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.rx_data_p (adc_data_p_s[l_inst]),
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.rx_data_n (adc_data_n_s[l_inst]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_ld (delay_ld[l_inst]),
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.delay_wdata (delay_wdata),
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.delay_rdata (delay_rdata_s[l_inst]),
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.delay_locked ());
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end
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endgenerate
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// over-range interface
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ad_lvds_in #(
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.BUFTYPE (PCORE_BUFTYPE),
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.IODELAY_CTRL (1),
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.IODELAY_GROUP (PCORE_IODELAY_GROUP))
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i_adc_or (
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.rx_clk (adc_clk_in),
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.rx_data_in_p (adc_or_in_p),
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.rx_data_in_n (adc_or_in_n),
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.rx_data_p (adc_or_p_s),
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.rx_data_n (adc_or_n_s),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_ld (delay_ld[12]),
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.delay_wdata (delay_wdata),
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.delay_rdata (delay_rdata_s[12]),
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.delay_locked (delay_locked));
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// clock input buffers and MMCM
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ad_serdes_clk #(
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.MMCM_DEVICE_TYPE (PCORE_DEVTYPE),
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.MMCM_CLKIN_PERIOD (2),
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.MMCM_VCO_DIV (6),
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.MMCM_VCO_MUL (12),
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.MMCM_CLK0_DIV (2),
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.MMCM_CLK1_DIV (8))
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i_serdes_clk (
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.mmcm_rst (mmcm_rst),
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.clk_in_p (adc_clk_in_p),
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.clk_in_n (adc_clk_in_n),
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.clk (adc_clk_in),
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.div_clk (adc_div_clk),
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.drp_clk (drp_clk),
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.drp_rst (drp_rst),
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.drp_sel (drp_sel),
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.drp_wr (drp_wr),
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.drp_addr (drp_addr),
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.drp_wdata (drp_wdata),
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.drp_rdata (drp_rdata),
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.drp_ready (drp_ready),
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.drp_locked (drp_locked));
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// input SERDES for data
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ad_serdes_in #(
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.DEVICE_TYPE(PCORE_DEVTYPE),
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.SERDES(1),
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.DATA_WIDTH(12),
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.PARALLEL_DATA_WIDTH(4))
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i_serdes_data (
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.rst(adc_rst),
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.clk(adc_clk_in),
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.div_clk(adc_div_clk),
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.data_s0(adc_data_s0),
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.data_s1(adc_data_s1),
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.data_s2(adc_data_s2),
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.data_s3(adc_data_s3),
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.data_s4(),
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.data_s5(),
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.data_s6(),
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.data_s7(),
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.data_in_p(adc_data_p_s),
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.data_in_n(adc_data_n_s));
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// input SERDES for overrange
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ad_serdes_in #(
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.DEVICE_TYPE(PCORE_DEVTYPE),
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.SERDES(1),
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.DATA_WIDTH(1),
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.PARALLEL_DATA_WIDTH(4))
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i_serdes_or (
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.rst(adc_rst),
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.clk(adc_clk_in),
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.div_clk(adc_div_clk),
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.data_s0(adc_or_s0),
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.data_s1(adc_or_s1),
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.data_s2(adc_or_s2),
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.data_s3(adc_or_s3),
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.data_s4(),
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.data_s5(),
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.data_s6(),
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.data_s7(),
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.data_in_p(adc_or_p_s),
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.data_in_n(adc_or_n_s));
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// adc status: adc is up, if both the MMCM and DELAY blocks are up
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always @(posedge adc_div_clk) begin
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if(adc_rst == 1'b1) begin
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adc_status_m1 <= 1'b0;
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adc_status <= 1'b0;
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end else begin
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adc_status_m1 <= drp_locked & delay_locked;
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end
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end
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endmodule
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