95 lines
3.9 KiB
Verilog
95 lines
3.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module ad_tdd_sync (
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clk, // system clock (100 Mhz)
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rstn,
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sync // re-synchronization signal
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);
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localparam PULSE_CNTR_WIDTH = 7;
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parameter TDD_SYNC_PERIOD = 100000000; // t_period * clk_freq - 1
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input clk;
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input rstn;
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output sync;
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// internal registers
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reg [(PULSE_CNTR_WIDTH-1):0] pulse_counter = {PULSE_CNTR_WIDTH{1'b1}};
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reg [31:0] sync_counter = 32'h0;
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reg sync_pulse = 1'b0;
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reg sync_period_eof = 1'b0;
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assign sync = sync_pulse;
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// a free running sync pulse generator
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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sync_counter <= 32'h0;
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sync_period_eof <= 1'b0;
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end else begin
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sync_counter <= (sync_counter < TDD_SYNC_PERIOD) ? (sync_counter + 1) : 32'b0;
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sync_period_eof <= (sync_counter == (TDD_SYNC_PERIOD - 1)) ? 1'b1 : 1'b0;
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end
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end
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// generate pulse with a specified width
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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pulse_counter <= 0;
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sync_pulse <= 0;
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end else begin
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pulse_counter <= (sync_pulse == 1'b1) ? pulse_counter + 1 : {PULSE_CNTR_WIDTH{1'h0}};
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if(sync_period_eof == 1'b1) begin
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sync_pulse <= 1'b1;
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end else if(pulse_counter == {PULSE_CNTR_WIDTH{1'b1}}) begin
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sync_pulse <= 1'b0;
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end
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end
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end
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endmodule
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