pluto_hdl_adi/library/common/ad_mem.v

84 lines
3.2 KiB
Verilog

// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
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// - Redistributions in binary form must reproduce the above copyright
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// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
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// - Use of the software either in source or binary form, must be run
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_mem (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
parameter DATA_WIDTH = 16;
parameter ADDRESS_WIDTH = 5;
localparam DW = DATA_WIDTH - 1;
localparam AW = ADDRESS_WIDTH - 1;
input clka;
input wea;
input [AW:0] addra;
input [DW:0] dina;
input clkb;
input [AW:0] addrb;
output [DW:0] doutb;
reg [DW:0] m_ram[0:((2**ADDRESS_WIDTH)-1)];
reg [DW:0] doutb;
always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end
always @(posedge clkb) begin
doutb <= m_ram[addrb];
end
endmodule
// ***************************************************************************
// ***************************************************************************