263 lines
8.2 KiB
Verilog
263 lines
8.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_mc_controller
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(
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input ref_clk, // 100 MHz
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input ctrl_data_clk,
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// physical interface
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output fmc_en_o,
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output pwm_ah_o,
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output pwm_al_o,
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output pwm_bh_o,
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output pwm_bl_o,
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output pwm_ch_o,
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output pwm_cl_o,
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output [3:0] gpo_o,
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// controller connections
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input pwm_a_i,
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input pwm_b_i,
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input pwm_c_i,
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// interconnection with other modules
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output[1:0] sensors_o,
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input [2:0] position_i,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [31:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [31:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready
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);
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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// internal registers
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reg [31:0] up_rdata = 'd0;
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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reg pwm_gen_clk = 'd0;
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//------------------------------------------------------------------------------
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//----------- Wires Declarations -----------------------------------------------
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//------------------------------------------------------------------------------
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// internal clocks & resets
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wire adc_rst;
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire up_rreq_s;
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wire up_wreq_s;
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wire [13:0] up_raddr_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_control_rdata_s;
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wire up_control_wack_s;
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wire up_control_rack_s;
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wire run_s;
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wire star_delta_s;
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wire dir_s;
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wire [10:0] pwm_open_s;
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wire [10:0] pwm_s;
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wire dpwm_ah_s;
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wire dpwm_al_s;
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wire dpwm_bh_s;
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wire dpwm_bl_s;
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wire dpwm_ch_s;
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wire dpwm_cl_s;
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wire foc_ctrl_s;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign adc_clk_o = ctrl_data_clk;
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assign ctrl_rst_o = !run_s;
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// monitor signals
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assign fmc_en_o = run_s;
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assign pwm_s = pwm_open_s ;
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assign pwm_ah_o = foc_ctrl_s ? !pwm_a_i : dpwm_ah_s;
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assign pwm_al_o = foc_ctrl_s ? pwm_a_i : dpwm_al_s;
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assign pwm_bh_o = foc_ctrl_s ? !pwm_b_i : dpwm_bh_s;
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assign pwm_bl_o = foc_ctrl_s ? pwm_b_i : dpwm_bl_s;
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assign pwm_ch_o = foc_ctrl_s ? !pwm_c_i : dpwm_ch_s;
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assign pwm_cl_o = foc_ctrl_s ? pwm_c_i : dpwm_cl_s;
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// clock generation
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always @(posedge ref_clk)
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begin
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pwm_gen_clk <= ~pwm_gen_clk; // generate 50 MHz clk
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if(up_rstn == 0) begin
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up_rdata <= 'd0;
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up_wack <= 'd0;
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up_rack <= 'd0;
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end else begin
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up_rdata <= up_control_rdata_s ;
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up_rack <= up_control_rack_s ;
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up_wack <= up_control_wack_s ;
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end
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end
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// main (device interface)
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motor_driver
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#( .PWM_BITS(11))
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motor_driver_inst(
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.clk_i(ctrl_data_clk),
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.pwm_clk_i(pwm_gen_clk),
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.rst_n_i(up_rstn) ,
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.run_i(run_s),
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.star_delta_i(star_delta_s),
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.dir_i(dir_s),
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.position_i(position_i),
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.pwm_duty_i(pwm_s),
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.AH_o(dpwm_ah_s),
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.BH_o(dpwm_bh_s),
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.CH_o(dpwm_ch_s),
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.AL_o(dpwm_al_s),
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.BL_o(dpwm_bl_s),
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.CL_o(dpwm_cl_s));
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control_registers control_reg_inst(
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_control_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_control_rdata_s),
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.up_rack (up_control_rack_s),
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.run_o(run_s),
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.break_o(),
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.dir_o(dir_s),
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.star_delta_o(star_delta_s),
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.sensors_o(sensors_o),
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.kp_o(),
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.ki_o(),
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.kd_o(),
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.kp1_o(),
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.ki1_o(),
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.kd1_o(),
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.gpo_o(gpo_o),
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.reference_speed_o(),
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.oloop_matlab_o(foc_ctrl_s),
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.err_i(32'h0),
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.calibrate_adcs_o(),
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.pwm_open_o(pwm_open_s));
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// up bus interface
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up_axi i_up_axi(
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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