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Lars-Peter Clausen 28801f2f37 common: a10soc: Use correct DDR memory reference clock type 
The DDR memory reference clock on the A10SoC development board is
differential. Currently the EMIF core it is configured for single-ended
configuration, which causes it to generate incorrect IOSTANDARD
constraints. Those incorrect constraints get overwritten again in
system_assign.tcl, so things are working, but this generates a warning when
building the design

Configure the EMIF core correctly and remove the manual constraint overwrite since
they are no longer necessary.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-08-07 17:42:17 +02:00
library axi_ad9671: Fix typo 2017-08-07 10:54:45 +01:00
projects common: a10soc: Use correct DDR memory reference clock type 2017-08-07 17:42:17 +02:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Update .gitignore 2016-12-19 15:37:05 +00:00
LICENSE license: GPL must be GPL v2 2017-05-31 18:18:45 +03:00
LICENSE_ADIBSD license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_GPL2 license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_LGPL license: Add top level license files 2017-05-29 09:57:39 +03:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-03-31 19:42:52 +03:00

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