144 lines
3.9 KiB
Verilog
144 lines
3.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dest_fifo_inf #(
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parameter ID_WIDTH = 3,
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parameter DATA_WIDTH = 64,
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parameter BEATS_PER_BURST_WIDTH = 4
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) (
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input clk,
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input resetn,
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input enable,
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output enabled,
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input req_valid,
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output req_ready,
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output [ID_WIDTH-1:0] response_id,
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output reg [ID_WIDTH-1:0] data_id = 'h0,
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input data_eot,
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input response_eot,
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input en,
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output reg [DATA_WIDTH-1:0] dout,
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output reg valid,
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output reg underflow,
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output xfer_req,
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output fifo_ready,
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input fifo_valid,
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input [DATA_WIDTH-1:0] fifo_data,
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input fifo_last,
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output response_valid,
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input response_ready,
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output response_resp_eot,
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output [1:0] response_resp
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);
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`include "inc_id.vh"
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reg active = 1'b0;
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// Last beat of the burst
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wire fifo_last_beat;
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// Last beat of the segment
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wire fifo_eot_beat;
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assign enabled = enable;
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assign fifo_ready = en & (fifo_valid | ~enable);
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// fifo_last == 1'b1 implies fifo_valid == 1'b1
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assign fifo_last_beat = fifo_ready & fifo_last;
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assign fifo_eot_beat = fifo_last_beat & data_eot;
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assign req_ready = fifo_eot_beat | ~active;
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assign xfer_req = active;
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always @(posedge clk) begin
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if (en) begin
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dout <= fifo_valid ? fifo_data : {DATA_WIDTH{1'b0}};
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valid <= fifo_valid & enable;
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underflow <= ~(fifo_valid & enable);
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end else begin
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valid <= 1'b0;
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underflow <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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data_id <= 'h00;
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end else if (fifo_last_beat == 1'b1) begin
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data_id <= inc_id(data_id);
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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active <= 1'b0;
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end else if (req_valid == 1'b1) begin
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active <= 1'b1;
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end else if (fifo_eot_beat == 1'b1) begin
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active <= 1'b0;
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end
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end
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response_generator #(
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.ID_WIDTH(ID_WIDTH)
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) i_response_generator (
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.clk(clk),
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.resetn(resetn),
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.enable(enable),
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.enabled(),
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.request_id(data_id),
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.response_id(response_id),
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.eot(response_eot),
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.resp_valid(response_valid),
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.resp_ready(response_ready),
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.resp_eot(response_resp_eot),
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.resp_resp(response_resp));
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endmodule
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