446 lines
19 KiB
Systemverilog
446 lines
19 KiB
Systemverilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_tdd_regmap #(
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parameter ID = 0,
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parameter CHANNEL_COUNT = 8,
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parameter DEFAULT_POLARITY = 8'h00,
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parameter REGISTER_WIDTH = 32,
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parameter BURST_COUNT_WIDTH = 32,
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parameter SYNC_INTERNAL = 1,
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parameter SYNC_EXTERNAL = 0,
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parameter SYNC_EXTERNAL_CDC = 0,
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parameter SYNC_COUNT_WIDTH = 64
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) (
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// tdd clock
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input logic tdd_clk,
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input logic tdd_resetn,
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// tdd interface control
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input axi_tdd_pkg::state_t tdd_cstate,
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output logic tdd_enable,
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output logic [CHANNEL_COUNT-1:0] tdd_channel_en,
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output logic [CHANNEL_COUNT-1:0] asy_tdd_channel_pol,
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output logic [BURST_COUNT_WIDTH-1:0] asy_tdd_burst_count,
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output logic [REGISTER_WIDTH-1:0] asy_tdd_startup_delay,
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output logic [REGISTER_WIDTH-1:0] asy_tdd_frame_length,
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output logic [REGISTER_WIDTH-1:0] asy_tdd_channel_on [0:CHANNEL_COUNT-1],
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output logic [REGISTER_WIDTH-1:0] asy_tdd_channel_off [0:CHANNEL_COUNT-1],
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output logic [SYNC_COUNT_WIDTH-1:0] asy_tdd_sync_period,
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output logic tdd_sync_rst,
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output logic tdd_sync_int,
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output logic tdd_sync_ext,
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output logic tdd_sync_soft,
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// bus interface
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input logic up_rstn,
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input logic up_clk,
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input logic up_wreq,
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input logic [ 7:0] up_waddr,
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input logic [31:0] up_wdata,
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output logic up_wack,
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input logic up_rreq,
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input logic [ 7:0] up_raddr,
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output logic [31:0] up_rdata,
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output logic up_rack
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);
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// package import
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import axi_tdd_pkg::*;
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// local params
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localparam CHANNEL_COUNT_EXTRA = CHANNEL_COUNT - 1;
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// internal registers
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logic [31:0] up_scratch;
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logic [ 1:0] up_tdd_cstate;
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logic up_tdd_enable;
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logic up_tdd_sync_rst;
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logic up_tdd_sync_int;
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logic up_tdd_sync_ext;
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logic up_tdd_sync_soft;
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logic [CHANNEL_COUNT-1:0] up_tdd_channel_en;
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logic [CHANNEL_COUNT-1:0] up_tdd_channel_pol;
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logic [BURST_COUNT_WIDTH-1:0] up_tdd_burst_count;
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logic [REGISTER_WIDTH-1:0] up_tdd_startup_delay;
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logic [REGISTER_WIDTH-1:0] up_tdd_frame_length;
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logic [REGISTER_WIDTH-1:0] up_tdd_channel_on [0:CHANNEL_COUNT-1];
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logic [REGISTER_WIDTH-1:0] up_tdd_channel_off [0:CHANNEL_COUNT-1];
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//internal wires
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logic [31:0] status_synth_params_s;
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logic [31:0] status_def_polarity_s;
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logic [31:0] up_tdd_channel_en_s;
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logic [31:0] up_tdd_channel_pol_s;
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logic [31:0] up_tdd_burst_count_s;
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logic [31:0] up_tdd_startup_delay_s;
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logic [31:0] up_tdd_frame_length_s;
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logic [63:0] up_tdd_sync_period_s;
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logic [31:0] up_tdd_channel_on_s [0:31];
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logic [31:0] up_tdd_channel_off_s [0:31];
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//initial values
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initial begin
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up_rdata = 32'b0;
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up_wack = 1'b0;
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up_rack = 1'b0;
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up_scratch = 32'b0;
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up_tdd_enable = 1'b0;
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up_tdd_sync_rst = 1'b0;
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up_tdd_sync_int = 1'b0;
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up_tdd_sync_ext = 1'b0;
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up_tdd_sync_soft = 1'b0;
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up_tdd_channel_en = '0;
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up_tdd_channel_pol = '0;
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up_tdd_burst_count = '0;
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up_tdd_startup_delay = '0;
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up_tdd_frame_length = '0;
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up_tdd_channel_on = '{default:0};
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up_tdd_channel_off = '{default:0};
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end
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//read-only synthesis parameters
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assign status_synth_params_s = {
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/*31:24 */ 1'b0, 7'(SYNC_COUNT_WIDTH),
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/*23:16 */ 2'b0, 6'(BURST_COUNT_WIDTH),
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/*15: 8 */ 2'b0, 6'(REGISTER_WIDTH),
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/* 7: 0 */ 1'(SYNC_EXTERNAL_CDC),
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1'(SYNC_EXTERNAL),
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1'(SYNC_INTERNAL),
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5'(CHANNEL_COUNT_EXTRA)};
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assign status_def_polarity_s = {{(32-CHANNEL_COUNT){1'b0}}, DEFAULT_POLARITY};
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// processor write interface
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 1'b0;
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up_scratch <= 32'b0;
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up_tdd_enable <= 1'b0;
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up_tdd_sync_rst <= 1'b0;
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up_tdd_sync_int <= 1'b0;
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up_tdd_sync_ext <= 1'b0;
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up_tdd_sync_soft <= 1'b0;
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up_tdd_channel_en <= '0;
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up_tdd_channel_pol <= '0;
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up_tdd_startup_delay <= '0;
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up_tdd_frame_length <= '0;
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up_tdd_burst_count <= '0;
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end else begin
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up_wack <= up_wreq;
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if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_SCRATCH)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_CONTROL)) begin
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up_tdd_sync_soft <= up_wdata[4];
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up_tdd_sync_ext <= up_wdata[3] & SYNC_EXTERNAL;
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up_tdd_sync_int <= up_wdata[2] & SYNC_INTERNAL;
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up_tdd_sync_rst <= up_wdata[1];
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up_tdd_enable <= up_wdata[0];
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end else begin
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up_tdd_sync_soft <= 1'b0;
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up_tdd_sync_ext <= up_tdd_sync_ext;
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up_tdd_sync_int <= up_tdd_sync_int;
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up_tdd_sync_rst <= up_tdd_sync_rst;
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up_tdd_enable <= up_tdd_enable;
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end
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if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_CH_ENABLE)) begin
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up_tdd_channel_en <= up_wdata[CHANNEL_COUNT-1:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_CH_POLARITY) && !up_tdd_enable) begin
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up_tdd_channel_pol <= up_wdata[CHANNEL_COUNT-1:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_BURST_COUNT) && !up_tdd_enable) begin
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up_tdd_burst_count <= up_wdata[BURST_COUNT_WIDTH-1:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_STARTUP_DELAY) && !up_tdd_enable) begin
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up_tdd_startup_delay <= up_wdata[REGISTER_WIDTH-1:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_FRAME_LENGTH) && !up_tdd_enable) begin
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up_tdd_frame_length <= up_wdata[REGISTER_WIDTH-1:0];
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end
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end
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end
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assign up_tdd_channel_en_s = {{(32-CHANNEL_COUNT){1'b0}}, up_tdd_channel_en};
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assign up_tdd_channel_pol_s = {{(32-CHANNEL_COUNT){1'b0}}, up_tdd_channel_pol};
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assign up_tdd_burst_count_s = {{(32-BURST_COUNT_WIDTH){1'b0}}, up_tdd_burst_count};
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assign up_tdd_startup_delay_s = {{(32-REGISTER_WIDTH){1'b0}}, up_tdd_startup_delay};
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assign up_tdd_frame_length_s = {{(32-REGISTER_WIDTH){1'b0}}, up_tdd_frame_length};
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// internal sync counter generation (low and high)
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generate
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if (SYNC_COUNT_WIDTH>32) begin
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logic [31:0] up_tdd_sync_period_low;
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logic [(SYNC_COUNT_WIDTH-32-1):0] up_tdd_sync_period_high;
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_tdd_sync_period_low <= 32'b0;
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up_tdd_sync_period_high <= '0;
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end else begin
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if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_SYNC_CNT_LOW) && !up_tdd_enable) begin
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up_tdd_sync_period_low <= up_wdata[31:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_SYNC_CNT_HIGH) && !up_tdd_enable) begin
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up_tdd_sync_period_high <= up_wdata[(SYNC_COUNT_WIDTH-32-1):0];
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end
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end
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end
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assign up_tdd_sync_period_s[31:0] = up_tdd_sync_period_low;
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assign up_tdd_sync_period_s[63:32] = {{(64-SYNC_COUNT_WIDTH){1'b0}}, up_tdd_sync_period_high};
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assign asy_tdd_sync_period = {up_tdd_sync_period_high, up_tdd_sync_period_low}; //skipping CDC
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end else begin
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if (SYNC_COUNT_WIDTH>0) begin
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logic [SYNC_COUNT_WIDTH-1:0] up_tdd_sync_period_low;
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_tdd_sync_period_low <= '0;
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end else begin
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if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_SYNC_CNT_LOW) && !up_tdd_enable) begin
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up_tdd_sync_period_low <= up_wdata[(SYNC_COUNT_WIDTH-1):0];
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end
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end
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end
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assign up_tdd_sync_period_s[31:0] = {{(32-SYNC_COUNT_WIDTH){1'b0}}, up_tdd_sync_period_low};
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assign up_tdd_sync_period_s[63:32] = 32'b0;
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assign asy_tdd_sync_period = up_tdd_sync_period_low; //skipping CDC
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end else begin
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assign up_tdd_sync_period_s[31:0] = 32'b0;
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assign up_tdd_sync_period_s[63:32] = 32'b0;
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assign asy_tdd_sync_period = '0;
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end
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end
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endgenerate
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// channel register generation
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genvar i;
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generate
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for (i=0; i<CHANNEL_COUNT; i=i+1) begin
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_tdd_channel_on[i] <= '0;
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up_tdd_channel_off[i] <= '0;
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end else begin
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if ((up_wreq == 1'b1) && (up_waddr == (ADDR_TDD_CH_ON + i*2)) && !up_tdd_enable) begin
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up_tdd_channel_on[i] <= up_wdata[REGISTER_WIDTH-1:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr == (ADDR_TDD_CH_OFF + i*2)) && !up_tdd_enable) begin
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up_tdd_channel_off[i] <= up_wdata[REGISTER_WIDTH-1:0];
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end
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end
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end
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assign up_tdd_channel_on_s[i] = {{(32-REGISTER_WIDTH){1'b0}}, up_tdd_channel_on[i]};
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assign up_tdd_channel_off_s[i] = {{(32-REGISTER_WIDTH){1'b0}}, up_tdd_channel_off[i]};
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end
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if (CHANNEL_COUNT<32) begin
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assign up_tdd_channel_on_s[CHANNEL_COUNT:31] = '{default:0};
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assign up_tdd_channel_off_s[CHANNEL_COUNT:31] = '{default:0};
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end
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endgenerate
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// processor read interface
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 1'b0;
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up_rdata <= 32'b0;
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end else begin
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up_rack <= up_rreq;
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if (up_rreq == 1'b1) begin
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case (up_raddr)
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ADDR_TDD_VERSION : up_rdata <= PCORE_VERSION;
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ADDR_TDD_ID : up_rdata <= ID[31:0];
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ADDR_TDD_SCRATCH : up_rdata <= up_scratch;
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ADDR_TDD_IDENTIFICATION : up_rdata <= PCORE_MAGIC;
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ADDR_TDD_INTERFACE : up_rdata <= status_synth_params_s;
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ADDR_TDD_DEF_POLARITY : up_rdata <= status_def_polarity_s;
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ADDR_TDD_CONTROL : up_rdata <= {27'b0, up_tdd_sync_soft,
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up_tdd_sync_ext,
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up_tdd_sync_int,
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up_tdd_sync_rst,
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up_tdd_enable};
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ADDR_TDD_CH_ENABLE : up_rdata <= up_tdd_channel_en_s;
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ADDR_TDD_CH_POLARITY : up_rdata <= up_tdd_channel_pol_s;
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ADDR_TDD_BURST_COUNT : up_rdata <= up_tdd_burst_count_s;
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ADDR_TDD_STARTUP_DELAY : up_rdata <= up_tdd_startup_delay_s;
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ADDR_TDD_FRAME_LENGTH : up_rdata <= up_tdd_frame_length_s;
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ADDR_TDD_SYNC_CNT_LOW : up_rdata <= up_tdd_sync_period_s[31:0];
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ADDR_TDD_SYNC_CNT_HIGH : up_rdata <= up_tdd_sync_period_s[63:32];
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ADDR_TDD_STATUS : up_rdata <= {30'b0, up_tdd_cstate};
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ADDR_TDD_CH_ON + 2*CH0 : up_rdata <= up_tdd_channel_on_s[CH0];
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ADDR_TDD_CH_OFF + 2*CH0 : up_rdata <= up_tdd_channel_off_s[CH0];
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ADDR_TDD_CH_ON + 2*CH1 : up_rdata <= up_tdd_channel_on_s[CH1];
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ADDR_TDD_CH_OFF + 2*CH1 : up_rdata <= up_tdd_channel_off_s[CH1];
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ADDR_TDD_CH_ON + 2*CH2 : up_rdata <= up_tdd_channel_on_s[CH2];
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ADDR_TDD_CH_OFF + 2*CH2 : up_rdata <= up_tdd_channel_off_s[CH2];
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ADDR_TDD_CH_ON + 2*CH3 : up_rdata <= up_tdd_channel_on_s[CH3];
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ADDR_TDD_CH_OFF + 2*CH3 : up_rdata <= up_tdd_channel_off_s[CH3];
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ADDR_TDD_CH_ON + 2*CH4 : up_rdata <= up_tdd_channel_on_s[CH4];
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ADDR_TDD_CH_OFF + 2*CH4 : up_rdata <= up_tdd_channel_off_s[CH4];
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ADDR_TDD_CH_ON + 2*CH5 : up_rdata <= up_tdd_channel_on_s[CH5];
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ADDR_TDD_CH_OFF + 2*CH5 : up_rdata <= up_tdd_channel_off_s[CH5];
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ADDR_TDD_CH_ON + 2*CH6 : up_rdata <= up_tdd_channel_on_s[CH6];
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ADDR_TDD_CH_OFF + 2*CH6 : up_rdata <= up_tdd_channel_off_s[CH6];
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ADDR_TDD_CH_ON + 2*CH7 : up_rdata <= up_tdd_channel_on_s[CH7];
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ADDR_TDD_CH_OFF + 2*CH7 : up_rdata <= up_tdd_channel_off_s[CH7];
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ADDR_TDD_CH_ON + 2*CH8 : up_rdata <= up_tdd_channel_on_s[CH8];
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ADDR_TDD_CH_OFF + 2*CH8 : up_rdata <= up_tdd_channel_off_s[CH8];
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ADDR_TDD_CH_ON + 2*CH9 : up_rdata <= up_tdd_channel_on_s[CH9];
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ADDR_TDD_CH_OFF + 2*CH9 : up_rdata <= up_tdd_channel_off_s[CH9];
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ADDR_TDD_CH_ON + 2*CH10 : up_rdata <= up_tdd_channel_on_s[CH10];
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ADDR_TDD_CH_OFF + 2*CH10 : up_rdata <= up_tdd_channel_off_s[CH10];
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ADDR_TDD_CH_ON + 2*CH11 : up_rdata <= up_tdd_channel_on_s[CH11];
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ADDR_TDD_CH_OFF + 2*CH11 : up_rdata <= up_tdd_channel_off_s[CH11];
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ADDR_TDD_CH_ON + 2*CH12 : up_rdata <= up_tdd_channel_on_s[CH12];
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ADDR_TDD_CH_OFF + 2*CH12 : up_rdata <= up_tdd_channel_off_s[CH12];
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ADDR_TDD_CH_ON + 2*CH13 : up_rdata <= up_tdd_channel_on_s[CH13];
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ADDR_TDD_CH_OFF + 2*CH13 : up_rdata <= up_tdd_channel_off_s[CH13];
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ADDR_TDD_CH_ON + 2*CH14 : up_rdata <= up_tdd_channel_on_s[CH14];
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ADDR_TDD_CH_OFF + 2*CH14 : up_rdata <= up_tdd_channel_off_s[CH14];
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ADDR_TDD_CH_ON + 2*CH15 : up_rdata <= up_tdd_channel_on_s[CH15];
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ADDR_TDD_CH_OFF + 2*CH15 : up_rdata <= up_tdd_channel_off_s[CH15];
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ADDR_TDD_CH_ON + 2*CH16 : up_rdata <= up_tdd_channel_on_s[CH16];
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ADDR_TDD_CH_OFF + 2*CH16 : up_rdata <= up_tdd_channel_off_s[CH16];
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ADDR_TDD_CH_ON + 2*CH17 : up_rdata <= up_tdd_channel_on_s[CH17];
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ADDR_TDD_CH_OFF + 2*CH17 : up_rdata <= up_tdd_channel_off_s[CH17];
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ADDR_TDD_CH_ON + 2*CH18 : up_rdata <= up_tdd_channel_on_s[CH18];
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ADDR_TDD_CH_OFF + 2*CH18 : up_rdata <= up_tdd_channel_off_s[CH18];
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ADDR_TDD_CH_ON + 2*CH19 : up_rdata <= up_tdd_channel_on_s[CH19];
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ADDR_TDD_CH_OFF + 2*CH19 : up_rdata <= up_tdd_channel_off_s[CH19];
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ADDR_TDD_CH_ON + 2*CH20 : up_rdata <= up_tdd_channel_on_s[CH20];
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ADDR_TDD_CH_OFF + 2*CH20 : up_rdata <= up_tdd_channel_off_s[CH20];
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ADDR_TDD_CH_ON + 2*CH21 : up_rdata <= up_tdd_channel_on_s[CH21];
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ADDR_TDD_CH_OFF + 2*CH21 : up_rdata <= up_tdd_channel_off_s[CH21];
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ADDR_TDD_CH_ON + 2*CH22 : up_rdata <= up_tdd_channel_on_s[CH22];
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ADDR_TDD_CH_OFF + 2*CH22 : up_rdata <= up_tdd_channel_off_s[CH22];
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ADDR_TDD_CH_ON + 2*CH23 : up_rdata <= up_tdd_channel_on_s[CH23];
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ADDR_TDD_CH_OFF + 2*CH23 : up_rdata <= up_tdd_channel_off_s[CH23];
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ADDR_TDD_CH_ON + 2*CH24 : up_rdata <= up_tdd_channel_on_s[CH24];
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ADDR_TDD_CH_OFF + 2*CH24 : up_rdata <= up_tdd_channel_off_s[CH24];
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ADDR_TDD_CH_ON + 2*CH25 : up_rdata <= up_tdd_channel_on_s[CH25];
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ADDR_TDD_CH_OFF + 2*CH25 : up_rdata <= up_tdd_channel_off_s[CH25];
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ADDR_TDD_CH_ON + 2*CH26 : up_rdata <= up_tdd_channel_on_s[CH26];
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ADDR_TDD_CH_OFF + 2*CH26 : up_rdata <= up_tdd_channel_off_s[CH26];
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ADDR_TDD_CH_ON + 2*CH27 : up_rdata <= up_tdd_channel_on_s[CH27];
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ADDR_TDD_CH_OFF + 2*CH27 : up_rdata <= up_tdd_channel_off_s[CH27];
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ADDR_TDD_CH_ON + 2*CH28 : up_rdata <= up_tdd_channel_on_s[CH28];
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|
ADDR_TDD_CH_OFF + 2*CH28 : up_rdata <= up_tdd_channel_off_s[CH28];
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ADDR_TDD_CH_ON + 2*CH29 : up_rdata <= up_tdd_channel_on_s[CH29];
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|
ADDR_TDD_CH_OFF + 2*CH29 : up_rdata <= up_tdd_channel_off_s[CH29];
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|
ADDR_TDD_CH_ON + 2*CH30 : up_rdata <= up_tdd_channel_on_s[CH30];
|
|
ADDR_TDD_CH_OFF + 2*CH30 : up_rdata <= up_tdd_channel_off_s[CH30];
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|
ADDR_TDD_CH_ON + 2*CH31 : up_rdata <= up_tdd_channel_on_s[CH31];
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ADDR_TDD_CH_OFF + 2*CH31 : up_rdata <= up_tdd_channel_off_s[CH31];
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default: up_rdata <= 32'b0;
|
|
endcase
|
|
end else begin
|
|
up_rdata <= 32'b0;
|
|
end
|
|
end
|
|
end
|
|
|
|
// control signals CDC
|
|
|
|
sync_bits #(
|
|
.NUM_OF_BITS (4),
|
|
.ASYNC_CLK (1)
|
|
) i_tdd_control_sync (
|
|
.in_bits ({up_tdd_sync_ext,
|
|
up_tdd_sync_int,
|
|
up_tdd_sync_rst,
|
|
up_tdd_enable}),
|
|
.out_resetn (tdd_resetn),
|
|
.out_clk (tdd_clk),
|
|
.out_bits ({tdd_sync_ext,
|
|
tdd_sync_int,
|
|
tdd_sync_rst,
|
|
tdd_enable}));
|
|
|
|
sync_event #(
|
|
.NUM_OF_EVENTS (1),
|
|
.ASYNC_CLK (1)
|
|
) i_tdd_soft_sync (
|
|
.in_clk (up_clk),
|
|
.in_event (up_tdd_sync_soft),
|
|
.out_clk (tdd_clk),
|
|
.out_event (tdd_sync_soft));
|
|
|
|
sync_bits #(
|
|
.NUM_OF_BITS (CHANNEL_COUNT),
|
|
.ASYNC_CLK (1)
|
|
) i_tdd_ch_en_sync (
|
|
.in_bits (up_tdd_channel_en),
|
|
.out_resetn (tdd_resetn),
|
|
.out_clk (tdd_clk),
|
|
.out_bits (tdd_channel_en));
|
|
|
|
sync_data #(
|
|
.NUM_OF_BITS (2),
|
|
.ASYNC_CLK (1)
|
|
) i_tdd_cstate_sync (
|
|
.in_clk (tdd_clk),
|
|
.in_data (tdd_cstate),
|
|
.out_clk (up_clk),
|
|
.out_data (up_tdd_cstate));
|
|
|
|
// skipping CDC for the rest of the registers since the register writes are gated with module enable
|
|
// furthermore, updating the async domain registers is also conditioned by the synchronized module enable
|
|
|
|
assign asy_tdd_burst_count = up_tdd_burst_count;
|
|
assign asy_tdd_startup_delay = up_tdd_startup_delay;
|
|
assign asy_tdd_frame_length = up_tdd_frame_length;
|
|
assign asy_tdd_channel_pol = up_tdd_channel_pol;
|
|
assign asy_tdd_channel_on = up_tdd_channel_on;
|
|
assign asy_tdd_channel_off = up_tdd_channel_off;
|
|
|
|
endmodule
|