72 lines
2.6 KiB
Verilog
72 lines
2.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_pad #(
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parameter NUM_OF_SAMPLES = 2,
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parameter IN_BITS_PER_SAMPLE = 16,
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parameter OUT_BITS_PER_SAMPLE = 16,
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parameter PADDING_TO_MSB_LSB_N = 0,
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parameter SIGN_EXTEND = 1
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) (
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input [NUM_OF_SAMPLES*IN_BITS_PER_SAMPLE-1:0] data_in,
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output reg [NUM_OF_SAMPLES*OUT_BITS_PER_SAMPLE-1:0] data_out
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);
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// Remove padding
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if (IN_BITS_PER_SAMPLE >= OUT_BITS_PER_SAMPLE) begin
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integer i;
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always @(*) begin
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for (i=0;i<NUM_OF_SAMPLES;i=i+1) begin
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if (PADDING_TO_MSB_LSB_N==1) begin
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data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
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data_in[i*IN_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE];
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end else begin
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data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
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data_in[((i+1)*IN_BITS_PER_SAMPLE)-1 -: OUT_BITS_PER_SAMPLE];
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end
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end
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end
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end
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// Add padding
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if (IN_BITS_PER_SAMPLE < OUT_BITS_PER_SAMPLE) begin
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integer i;
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always @(*) begin
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for (i=0;i<NUM_OF_SAMPLES;i=i+1) begin
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if (PADDING_TO_MSB_LSB_N==1) begin
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data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
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{{OUT_BITS_PER_SAMPLE-IN_BITS_PER_SAMPLE{data_in[(i+1)*IN_BITS_PER_SAMPLE-1]&SIGN_EXTEND[0]}},
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data_in[i*IN_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE]};
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end else begin
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data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
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{data_in[((i+1)*IN_BITS_PER_SAMPLE)-1 -: OUT_BITS_PER_SAMPLE],
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{OUT_BITS_PER_SAMPLE-IN_BITS_PER_SAMPLE{1'b0}}};
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end
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end
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end
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end
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endmodule
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