4348 lines
141 KiB
Verilog
4348 lines
141 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// AUTO GENERATED BY axi_adxcvr.pl, DO NOT MODIFY!
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`timescale 1ns/1ps
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module axi_adxcvr #(
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// parameters
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parameter integer ID = 0,
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parameter integer NUM_OF_LANES = 8,
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parameter integer XCVR_TYPE = 0,
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parameter integer LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter [15:0] FPGA_VOLTAGE = 0,
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parameter integer TX_OR_RX_N = 0,
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parameter integer QPLL_ENABLE = 1,
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parameter LPM_OR_DFE_N = 1,
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parameter [ 2:0] RATE = 3'd0,
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parameter [ 4:0] TX_DIFFCTRL = 5'd8,
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parameter [ 4:0] TX_POSTCURSOR = 5'd0,
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parameter [ 4:0] TX_PRECURSOR = 5'd0,
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parameter [ 1:0] SYS_CLK_SEL = 2'd3,
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parameter [ 2:0] OUT_CLK_SEL = 3'd4
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) (
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output up_cm_enb_0,
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output [11:0] up_cm_addr_0,
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output up_cm_wr_0,
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output [15:0] up_cm_wdata_0,
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input [15:0] up_cm_rdata_0,
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input up_cm_ready_0,
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output up_es_enb_0,
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output [11:0] up_es_addr_0,
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output up_es_wr_0,
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output up_es_reset_0,
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output [15:0] up_es_wdata_0,
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input [15:0] up_es_rdata_0,
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input up_es_ready_0,
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input up_ch_pll_locked_0,
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output up_ch_rst_0,
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output up_ch_user_ready_0,
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input up_ch_rst_done_0,
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output up_ch_prbsforceerr_0,
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output [ 3:0] up_ch_prbssel_0,
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output up_ch_prbscntreset_0,
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input up_ch_prbserr_0,
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input up_ch_prbslocked_0,
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input [ 1:0] up_ch_bufstatus_0,
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output up_ch_bufstatus_rst_0,
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output up_ch_lpm_dfe_n_0,
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output [ 2:0] up_ch_rate_0,
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output [ 1:0] up_ch_sys_clk_sel_0,
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output [ 2:0] up_ch_out_clk_sel_0,
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output [ 4:0] up_ch_tx_diffctrl_0,
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output [ 4:0] up_ch_tx_postcursor_0,
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output [ 4:0] up_ch_tx_precursor_0,
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output up_ch_enb_0,
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output [11:0] up_ch_addr_0,
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output up_ch_wr_0,
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output [15:0] up_ch_wdata_0,
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input [15:0] up_ch_rdata_0,
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input up_ch_ready_0,
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output up_es_enb_1,
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output [11:0] up_es_addr_1,
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output up_es_wr_1,
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output up_es_reset_1,
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output [15:0] up_es_wdata_1,
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input [15:0] up_es_rdata_1,
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input up_es_ready_1,
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input up_ch_pll_locked_1,
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output up_ch_rst_1,
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output up_ch_user_ready_1,
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input up_ch_rst_done_1,
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output up_ch_prbsforceerr_1,
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output [ 3:0] up_ch_prbssel_1,
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output up_ch_prbscntreset_1,
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input up_ch_prbserr_1,
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input up_ch_prbslocked_1,
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input [ 1:0] up_ch_bufstatus_1,
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output up_ch_bufstatus_rst_1,
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output up_ch_lpm_dfe_n_1,
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output [ 2:0] up_ch_rate_1,
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output [ 1:0] up_ch_sys_clk_sel_1,
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output [ 2:0] up_ch_out_clk_sel_1,
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output [ 4:0] up_ch_tx_diffctrl_1,
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output [ 4:0] up_ch_tx_postcursor_1,
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output [ 4:0] up_ch_tx_precursor_1,
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output up_ch_enb_1,
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output [11:0] up_ch_addr_1,
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output up_ch_wr_1,
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output [15:0] up_ch_wdata_1,
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input [15:0] up_ch_rdata_1,
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input up_ch_ready_1,
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output up_es_enb_2,
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output [11:0] up_es_addr_2,
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output up_es_wr_2,
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output up_es_reset_2,
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output [15:0] up_es_wdata_2,
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input [15:0] up_es_rdata_2,
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input up_es_ready_2,
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input up_ch_pll_locked_2,
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output up_ch_rst_2,
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output up_ch_user_ready_2,
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input up_ch_rst_done_2,
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output up_ch_prbsforceerr_2,
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output [ 3:0] up_ch_prbssel_2,
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output up_ch_prbscntreset_2,
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input up_ch_prbserr_2,
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input up_ch_prbslocked_2,
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input [ 1:0] up_ch_bufstatus_2,
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output up_ch_bufstatus_rst_2,
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output up_ch_lpm_dfe_n_2,
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output [ 2:0] up_ch_rate_2,
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output [ 1:0] up_ch_sys_clk_sel_2,
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output [ 2:0] up_ch_out_clk_sel_2,
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output [ 4:0] up_ch_tx_diffctrl_2,
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output [ 4:0] up_ch_tx_postcursor_2,
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output [ 4:0] up_ch_tx_precursor_2,
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output up_ch_enb_2,
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output [11:0] up_ch_addr_2,
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output up_ch_wr_2,
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output [15:0] up_ch_wdata_2,
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input [15:0] up_ch_rdata_2,
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input up_ch_ready_2,
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output up_es_enb_3,
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output [11:0] up_es_addr_3,
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output up_es_wr_3,
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output up_es_reset_3,
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output [15:0] up_es_wdata_3,
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input [15:0] up_es_rdata_3,
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input up_es_ready_3,
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input up_ch_pll_locked_3,
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output up_ch_rst_3,
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output up_ch_user_ready_3,
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input up_ch_rst_done_3,
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output up_ch_prbsforceerr_3,
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output [ 3:0] up_ch_prbssel_3,
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output up_ch_prbscntreset_3,
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input up_ch_prbserr_3,
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input up_ch_prbslocked_3,
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input [ 1:0] up_ch_bufstatus_3,
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output up_ch_bufstatus_rst_3,
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output up_ch_lpm_dfe_n_3,
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output [ 2:0] up_ch_rate_3,
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output [ 1:0] up_ch_sys_clk_sel_3,
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output [ 2:0] up_ch_out_clk_sel_3,
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output [ 4:0] up_ch_tx_diffctrl_3,
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output [ 4:0] up_ch_tx_postcursor_3,
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output [ 4:0] up_ch_tx_precursor_3,
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output up_ch_enb_3,
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output [11:0] up_ch_addr_3,
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output up_ch_wr_3,
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output [15:0] up_ch_wdata_3,
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input [15:0] up_ch_rdata_3,
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input up_ch_ready_3,
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output up_cm_enb_4,
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output [11:0] up_cm_addr_4,
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output up_cm_wr_4,
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output [15:0] up_cm_wdata_4,
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input [15:0] up_cm_rdata_4,
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input up_cm_ready_4,
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output up_es_enb_4,
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output [11:0] up_es_addr_4,
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output up_es_wr_4,
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output up_es_reset_4,
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output [15:0] up_es_wdata_4,
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input [15:0] up_es_rdata_4,
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input up_es_ready_4,
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input up_ch_pll_locked_4,
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output up_ch_rst_4,
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output up_ch_user_ready_4,
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input up_ch_rst_done_4,
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output up_ch_prbsforceerr_4,
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output [ 3:0] up_ch_prbssel_4,
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output up_ch_prbscntreset_4,
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input up_ch_prbserr_4,
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input up_ch_prbslocked_4,
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input [ 1:0] up_ch_bufstatus_4,
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output up_ch_bufstatus_rst_4,
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output up_ch_lpm_dfe_n_4,
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output [ 2:0] up_ch_rate_4,
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output [ 1:0] up_ch_sys_clk_sel_4,
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output [ 2:0] up_ch_out_clk_sel_4,
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output [ 4:0] up_ch_tx_diffctrl_4,
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output [ 4:0] up_ch_tx_postcursor_4,
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output [ 4:0] up_ch_tx_precursor_4,
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output up_ch_enb_4,
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output [11:0] up_ch_addr_4,
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output up_ch_wr_4,
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output [15:0] up_ch_wdata_4,
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input [15:0] up_ch_rdata_4,
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input up_ch_ready_4,
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output up_es_enb_5,
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output [11:0] up_es_addr_5,
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output up_es_wr_5,
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output up_es_reset_5,
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output [15:0] up_es_wdata_5,
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input [15:0] up_es_rdata_5,
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input up_es_ready_5,
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input up_ch_pll_locked_5,
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output up_ch_rst_5,
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output up_ch_user_ready_5,
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input up_ch_rst_done_5,
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output up_ch_prbsforceerr_5,
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output [ 3:0] up_ch_prbssel_5,
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output up_ch_prbscntreset_5,
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input up_ch_prbserr_5,
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input up_ch_prbslocked_5,
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input [ 1:0] up_ch_bufstatus_5,
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output up_ch_bufstatus_rst_5,
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output up_ch_lpm_dfe_n_5,
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output [ 2:0] up_ch_rate_5,
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output [ 1:0] up_ch_sys_clk_sel_5,
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output [ 2:0] up_ch_out_clk_sel_5,
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output [ 4:0] up_ch_tx_diffctrl_5,
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output [ 4:0] up_ch_tx_postcursor_5,
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output [ 4:0] up_ch_tx_precursor_5,
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output up_ch_enb_5,
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output [11:0] up_ch_addr_5,
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output up_ch_wr_5,
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output [15:0] up_ch_wdata_5,
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input [15:0] up_ch_rdata_5,
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input up_ch_ready_5,
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output up_es_enb_6,
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output [11:0] up_es_addr_6,
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output up_es_wr_6,
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output up_es_reset_6,
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output [15:0] up_es_wdata_6,
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input [15:0] up_es_rdata_6,
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input up_es_ready_6,
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input up_ch_pll_locked_6,
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output up_ch_rst_6,
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output up_ch_user_ready_6,
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input up_ch_rst_done_6,
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output up_ch_prbsforceerr_6,
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output [ 3:0] up_ch_prbssel_6,
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output up_ch_prbscntreset_6,
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input up_ch_prbserr_6,
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input up_ch_prbslocked_6,
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input [ 1:0] up_ch_bufstatus_6,
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output up_ch_bufstatus_rst_6,
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output up_ch_lpm_dfe_n_6,
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output [ 2:0] up_ch_rate_6,
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output [ 1:0] up_ch_sys_clk_sel_6,
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output [ 2:0] up_ch_out_clk_sel_6,
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output [ 4:0] up_ch_tx_diffctrl_6,
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output [ 4:0] up_ch_tx_postcursor_6,
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output [ 4:0] up_ch_tx_precursor_6,
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output up_ch_enb_6,
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output [11:0] up_ch_addr_6,
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output up_ch_wr_6,
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output [15:0] up_ch_wdata_6,
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input [15:0] up_ch_rdata_6,
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input up_ch_ready_6,
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output up_es_enb_7,
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output [11:0] up_es_addr_7,
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output up_es_wr_7,
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output up_es_reset_7,
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output [15:0] up_es_wdata_7,
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input [15:0] up_es_rdata_7,
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input up_es_ready_7,
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input up_ch_pll_locked_7,
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output up_ch_rst_7,
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output up_ch_user_ready_7,
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input up_ch_rst_done_7,
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output up_ch_prbsforceerr_7,
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output [ 3:0] up_ch_prbssel_7,
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output up_ch_prbscntreset_7,
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input up_ch_prbserr_7,
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input up_ch_prbslocked_7,
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input [ 1:0] up_ch_bufstatus_7,
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output up_ch_bufstatus_rst_7,
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output up_ch_lpm_dfe_n_7,
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output [ 2:0] up_ch_rate_7,
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output [ 1:0] up_ch_sys_clk_sel_7,
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output [ 2:0] up_ch_out_clk_sel_7,
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output [ 4:0] up_ch_tx_diffctrl_7,
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output [ 4:0] up_ch_tx_postcursor_7,
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output [ 4:0] up_ch_tx_precursor_7,
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output up_ch_enb_7,
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output [11:0] up_ch_addr_7,
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output up_ch_wr_7,
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output [15:0] up_ch_wdata_7,
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input [15:0] up_ch_rdata_7,
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input up_ch_ready_7,
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output up_cm_enb_8,
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output [11:0] up_cm_addr_8,
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output up_cm_wr_8,
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output [15:0] up_cm_wdata_8,
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input [15:0] up_cm_rdata_8,
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input up_cm_ready_8,
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output up_es_enb_8,
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output [11:0] up_es_addr_8,
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output up_es_wr_8,
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output up_es_reset_8,
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output [15:0] up_es_wdata_8,
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input [15:0] up_es_rdata_8,
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input up_es_ready_8,
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input up_ch_pll_locked_8,
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output up_ch_rst_8,
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output up_ch_user_ready_8,
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input up_ch_rst_done_8,
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output up_ch_prbsforceerr_8,
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output [ 3:0] up_ch_prbssel_8,
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output up_ch_prbscntreset_8,
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input up_ch_prbserr_8,
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input up_ch_prbslocked_8,
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input [ 1:0] up_ch_bufstatus_8,
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output up_ch_bufstatus_rst_8,
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output up_ch_lpm_dfe_n_8,
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output [ 2:0] up_ch_rate_8,
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output [ 1:0] up_ch_sys_clk_sel_8,
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output [ 2:0] up_ch_out_clk_sel_8,
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output [ 4:0] up_ch_tx_diffctrl_8,
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output [ 4:0] up_ch_tx_postcursor_8,
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output [ 4:0] up_ch_tx_precursor_8,
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output up_ch_enb_8,
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output [11:0] up_ch_addr_8,
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output up_ch_wr_8,
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output [15:0] up_ch_wdata_8,
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input [15:0] up_ch_rdata_8,
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input up_ch_ready_8,
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output up_es_enb_9,
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output [11:0] up_es_addr_9,
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output up_es_wr_9,
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output up_es_reset_9,
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output [15:0] up_es_wdata_9,
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input [15:0] up_es_rdata_9,
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input up_es_ready_9,
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input up_ch_pll_locked_9,
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output up_ch_rst_9,
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output up_ch_user_ready_9,
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input up_ch_rst_done_9,
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output up_ch_prbsforceerr_9,
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output [ 3:0] up_ch_prbssel_9,
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output up_ch_prbscntreset_9,
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input up_ch_prbserr_9,
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input up_ch_prbslocked_9,
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input [ 1:0] up_ch_bufstatus_9,
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output up_ch_bufstatus_rst_9,
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output up_ch_lpm_dfe_n_9,
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output [ 2:0] up_ch_rate_9,
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output [ 1:0] up_ch_sys_clk_sel_9,
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output [ 2:0] up_ch_out_clk_sel_9,
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output [ 4:0] up_ch_tx_diffctrl_9,
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output [ 4:0] up_ch_tx_postcursor_9,
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output [ 4:0] up_ch_tx_precursor_9,
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output up_ch_enb_9,
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output [11:0] up_ch_addr_9,
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output up_ch_wr_9,
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output [15:0] up_ch_wdata_9,
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input [15:0] up_ch_rdata_9,
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input up_ch_ready_9,
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output up_es_enb_10,
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output [11:0] up_es_addr_10,
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output up_es_wr_10,
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output up_es_reset_10,
|
|
output [15:0] up_es_wdata_10,
|
|
input [15:0] up_es_rdata_10,
|
|
input up_es_ready_10,
|
|
|
|
input up_ch_pll_locked_10,
|
|
output up_ch_rst_10,
|
|
output up_ch_user_ready_10,
|
|
input up_ch_rst_done_10,
|
|
output up_ch_prbsforceerr_10,
|
|
output [ 3:0] up_ch_prbssel_10,
|
|
output up_ch_prbscntreset_10,
|
|
input up_ch_prbserr_10,
|
|
input up_ch_prbslocked_10,
|
|
input [ 1:0] up_ch_bufstatus_10,
|
|
output up_ch_bufstatus_rst_10,
|
|
output up_ch_lpm_dfe_n_10,
|
|
output [ 2:0] up_ch_rate_10,
|
|
output [ 1:0] up_ch_sys_clk_sel_10,
|
|
output [ 2:0] up_ch_out_clk_sel_10,
|
|
output [ 4:0] up_ch_tx_diffctrl_10,
|
|
output [ 4:0] up_ch_tx_postcursor_10,
|
|
output [ 4:0] up_ch_tx_precursor_10,
|
|
output up_ch_enb_10,
|
|
output [11:0] up_ch_addr_10,
|
|
output up_ch_wr_10,
|
|
output [15:0] up_ch_wdata_10,
|
|
input [15:0] up_ch_rdata_10,
|
|
input up_ch_ready_10,
|
|
|
|
output up_es_enb_11,
|
|
output [11:0] up_es_addr_11,
|
|
output up_es_wr_11,
|
|
output up_es_reset_11,
|
|
output [15:0] up_es_wdata_11,
|
|
input [15:0] up_es_rdata_11,
|
|
input up_es_ready_11,
|
|
|
|
input up_ch_pll_locked_11,
|
|
output up_ch_rst_11,
|
|
output up_ch_user_ready_11,
|
|
input up_ch_rst_done_11,
|
|
output up_ch_prbsforceerr_11,
|
|
output [ 3:0] up_ch_prbssel_11,
|
|
output up_ch_prbscntreset_11,
|
|
input up_ch_prbserr_11,
|
|
input up_ch_prbslocked_11,
|
|
input [ 1:0] up_ch_bufstatus_11,
|
|
output up_ch_bufstatus_rst_11,
|
|
output up_ch_lpm_dfe_n_11,
|
|
output [ 2:0] up_ch_rate_11,
|
|
output [ 1:0] up_ch_sys_clk_sel_11,
|
|
output [ 2:0] up_ch_out_clk_sel_11,
|
|
output [ 4:0] up_ch_tx_diffctrl_11,
|
|
output [ 4:0] up_ch_tx_postcursor_11,
|
|
output [ 4:0] up_ch_tx_precursor_11,
|
|
output up_ch_enb_11,
|
|
output [11:0] up_ch_addr_11,
|
|
output up_ch_wr_11,
|
|
output [15:0] up_ch_wdata_11,
|
|
input [15:0] up_ch_rdata_11,
|
|
input up_ch_ready_11,
|
|
|
|
output up_cm_enb_12,
|
|
output [11:0] up_cm_addr_12,
|
|
output up_cm_wr_12,
|
|
output [15:0] up_cm_wdata_12,
|
|
input [15:0] up_cm_rdata_12,
|
|
input up_cm_ready_12,
|
|
|
|
output up_es_enb_12,
|
|
output [11:0] up_es_addr_12,
|
|
output up_es_wr_12,
|
|
output up_es_reset_12,
|
|
output [15:0] up_es_wdata_12,
|
|
input [15:0] up_es_rdata_12,
|
|
input up_es_ready_12,
|
|
|
|
input up_ch_pll_locked_12,
|
|
output up_ch_rst_12,
|
|
output up_ch_user_ready_12,
|
|
input up_ch_rst_done_12,
|
|
output up_ch_prbsforceerr_12,
|
|
output [ 3:0] up_ch_prbssel_12,
|
|
output up_ch_prbscntreset_12,
|
|
input up_ch_prbserr_12,
|
|
input up_ch_prbslocked_12,
|
|
input [ 1:0] up_ch_bufstatus_12,
|
|
output up_ch_bufstatus_rst_12,
|
|
output up_ch_lpm_dfe_n_12,
|
|
output [ 2:0] up_ch_rate_12,
|
|
output [ 1:0] up_ch_sys_clk_sel_12,
|
|
output [ 2:0] up_ch_out_clk_sel_12,
|
|
output [ 4:0] up_ch_tx_diffctrl_12,
|
|
output [ 4:0] up_ch_tx_postcursor_12,
|
|
output [ 4:0] up_ch_tx_precursor_12,
|
|
output up_ch_enb_12,
|
|
output [11:0] up_ch_addr_12,
|
|
output up_ch_wr_12,
|
|
output [15:0] up_ch_wdata_12,
|
|
input [15:0] up_ch_rdata_12,
|
|
input up_ch_ready_12,
|
|
|
|
output up_es_enb_13,
|
|
output [11:0] up_es_addr_13,
|
|
output up_es_wr_13,
|
|
output up_es_reset_13,
|
|
output [15:0] up_es_wdata_13,
|
|
input [15:0] up_es_rdata_13,
|
|
input up_es_ready_13,
|
|
|
|
input up_ch_pll_locked_13,
|
|
output up_ch_rst_13,
|
|
output up_ch_user_ready_13,
|
|
input up_ch_rst_done_13,
|
|
output up_ch_prbsforceerr_13,
|
|
output [ 3:0] up_ch_prbssel_13,
|
|
output up_ch_prbscntreset_13,
|
|
input up_ch_prbserr_13,
|
|
input up_ch_prbslocked_13,
|
|
input [ 1:0] up_ch_bufstatus_13,
|
|
output up_ch_bufstatus_rst_13,
|
|
output up_ch_lpm_dfe_n_13,
|
|
output [ 2:0] up_ch_rate_13,
|
|
output [ 1:0] up_ch_sys_clk_sel_13,
|
|
output [ 2:0] up_ch_out_clk_sel_13,
|
|
output [ 4:0] up_ch_tx_diffctrl_13,
|
|
output [ 4:0] up_ch_tx_postcursor_13,
|
|
output [ 4:0] up_ch_tx_precursor_13,
|
|
output up_ch_enb_13,
|
|
output [11:0] up_ch_addr_13,
|
|
output up_ch_wr_13,
|
|
output [15:0] up_ch_wdata_13,
|
|
input [15:0] up_ch_rdata_13,
|
|
input up_ch_ready_13,
|
|
|
|
output up_es_enb_14,
|
|
output [11:0] up_es_addr_14,
|
|
output up_es_wr_14,
|
|
output up_es_reset_14,
|
|
output [15:0] up_es_wdata_14,
|
|
input [15:0] up_es_rdata_14,
|
|
input up_es_ready_14,
|
|
|
|
input up_ch_pll_locked_14,
|
|
output up_ch_rst_14,
|
|
output up_ch_user_ready_14,
|
|
input up_ch_rst_done_14,
|
|
output up_ch_prbsforceerr_14,
|
|
output [ 3:0] up_ch_prbssel_14,
|
|
output up_ch_prbscntreset_14,
|
|
input up_ch_prbserr_14,
|
|
input up_ch_prbslocked_14,
|
|
input [ 1:0] up_ch_bufstatus_14,
|
|
output up_ch_bufstatus_rst_14,
|
|
output up_ch_lpm_dfe_n_14,
|
|
output [ 2:0] up_ch_rate_14,
|
|
output [ 1:0] up_ch_sys_clk_sel_14,
|
|
output [ 2:0] up_ch_out_clk_sel_14,
|
|
output [ 4:0] up_ch_tx_diffctrl_14,
|
|
output [ 4:0] up_ch_tx_postcursor_14,
|
|
output [ 4:0] up_ch_tx_precursor_14,
|
|
output up_ch_enb_14,
|
|
output [11:0] up_ch_addr_14,
|
|
output up_ch_wr_14,
|
|
output [15:0] up_ch_wdata_14,
|
|
input [15:0] up_ch_rdata_14,
|
|
input up_ch_ready_14,
|
|
|
|
output up_es_enb_15,
|
|
output [11:0] up_es_addr_15,
|
|
output up_es_wr_15,
|
|
output up_es_reset_15,
|
|
output [15:0] up_es_wdata_15,
|
|
input [15:0] up_es_rdata_15,
|
|
input up_es_ready_15,
|
|
|
|
input up_ch_pll_locked_15,
|
|
output up_ch_rst_15,
|
|
output up_ch_user_ready_15,
|
|
input up_ch_rst_done_15,
|
|
output up_ch_prbsforceerr_15,
|
|
output [ 3:0] up_ch_prbssel_15,
|
|
output up_ch_prbscntreset_15,
|
|
input up_ch_prbserr_15,
|
|
input up_ch_prbslocked_15,
|
|
input [ 1:0] up_ch_bufstatus_15,
|
|
output up_ch_bufstatus_rst_15,
|
|
output up_ch_lpm_dfe_n_15,
|
|
output [ 2:0] up_ch_rate_15,
|
|
output [ 1:0] up_ch_sys_clk_sel_15,
|
|
output [ 2:0] up_ch_out_clk_sel_15,
|
|
output [ 4:0] up_ch_tx_diffctrl_15,
|
|
output [ 4:0] up_ch_tx_postcursor_15,
|
|
output [ 4:0] up_ch_tx_precursor_15,
|
|
output up_ch_enb_15,
|
|
output [11:0] up_ch_addr_15,
|
|
output up_ch_wr_15,
|
|
output [15:0] up_ch_wdata_15,
|
|
input [15:0] up_ch_rdata_15,
|
|
input up_ch_ready_15,
|
|
|
|
output up_cm_enb_16,
|
|
output [11:0] up_cm_addr_16,
|
|
output up_cm_wr_16,
|
|
output [15:0] up_cm_wdata_16,
|
|
input [15:0] up_cm_rdata_16,
|
|
input up_cm_ready_16,
|
|
|
|
output up_es_enb_16,
|
|
output [11:0] up_es_addr_16,
|
|
output up_es_wr_16,
|
|
output up_es_reset_16,
|
|
output [15:0] up_es_wdata_16,
|
|
input [15:0] up_es_rdata_16,
|
|
input up_es_ready_16,
|
|
|
|
input up_ch_pll_locked_16,
|
|
output up_ch_rst_16,
|
|
output up_ch_user_ready_16,
|
|
input up_ch_rst_done_16,
|
|
output up_ch_prbsforceerr_16,
|
|
output [ 3:0] up_ch_prbssel_16,
|
|
output up_ch_prbscntreset_16,
|
|
input up_ch_prbserr_16,
|
|
input up_ch_prbslocked_16,
|
|
input [ 1:0] up_ch_bufstatus_16,
|
|
output up_ch_bufstatus_rst_16,
|
|
output up_ch_lpm_dfe_n_16,
|
|
output [ 2:0] up_ch_rate_16,
|
|
output [ 1:0] up_ch_sys_clk_sel_16,
|
|
output [ 2:0] up_ch_out_clk_sel_16,
|
|
output [ 4:0] up_ch_tx_diffctrl_16,
|
|
output [ 4:0] up_ch_tx_postcursor_16,
|
|
output [ 4:0] up_ch_tx_precursor_16,
|
|
output up_ch_enb_16,
|
|
output [11:0] up_ch_addr_16,
|
|
output up_ch_wr_16,
|
|
output [15:0] up_ch_wdata_16,
|
|
input [15:0] up_ch_rdata_16,
|
|
input up_ch_ready_16,
|
|
|
|
output up_es_enb_17,
|
|
output [11:0] up_es_addr_17,
|
|
output up_es_wr_17,
|
|
output up_es_reset_17,
|
|
output [15:0] up_es_wdata_17,
|
|
input [15:0] up_es_rdata_17,
|
|
input up_es_ready_17,
|
|
|
|
input up_ch_pll_locked_17,
|
|
output up_ch_rst_17,
|
|
output up_ch_user_ready_17,
|
|
input up_ch_rst_done_17,
|
|
output up_ch_prbsforceerr_17,
|
|
output [ 3:0] up_ch_prbssel_17,
|
|
output up_ch_prbscntreset_17,
|
|
input up_ch_prbserr_17,
|
|
input up_ch_prbslocked_17,
|
|
input [ 1:0] up_ch_bufstatus_17,
|
|
output up_ch_bufstatus_rst_17,
|
|
output up_ch_lpm_dfe_n_17,
|
|
output [ 2:0] up_ch_rate_17,
|
|
output [ 1:0] up_ch_sys_clk_sel_17,
|
|
output [ 2:0] up_ch_out_clk_sel_17,
|
|
output [ 4:0] up_ch_tx_diffctrl_17,
|
|
output [ 4:0] up_ch_tx_postcursor_17,
|
|
output [ 4:0] up_ch_tx_precursor_17,
|
|
output up_ch_enb_17,
|
|
output [11:0] up_ch_addr_17,
|
|
output up_ch_wr_17,
|
|
output [15:0] up_ch_wdata_17,
|
|
input [15:0] up_ch_rdata_17,
|
|
input up_ch_ready_17,
|
|
|
|
output up_es_enb_18,
|
|
output [11:0] up_es_addr_18,
|
|
output up_es_wr_18,
|
|
output up_es_reset_18,
|
|
output [15:0] up_es_wdata_18,
|
|
input [15:0] up_es_rdata_18,
|
|
input up_es_ready_18,
|
|
|
|
input up_ch_pll_locked_18,
|
|
output up_ch_rst_18,
|
|
output up_ch_user_ready_18,
|
|
input up_ch_rst_done_18,
|
|
output up_ch_prbsforceerr_18,
|
|
output [ 3:0] up_ch_prbssel_18,
|
|
output up_ch_prbscntreset_18,
|
|
input up_ch_prbserr_18,
|
|
input up_ch_prbslocked_18,
|
|
input [ 1:0] up_ch_bufstatus_18,
|
|
output up_ch_bufstatus_rst_18,
|
|
output up_ch_lpm_dfe_n_18,
|
|
output [ 2:0] up_ch_rate_18,
|
|
output [ 1:0] up_ch_sys_clk_sel_18,
|
|
output [ 2:0] up_ch_out_clk_sel_18,
|
|
output [ 4:0] up_ch_tx_diffctrl_18,
|
|
output [ 4:0] up_ch_tx_postcursor_18,
|
|
output [ 4:0] up_ch_tx_precursor_18,
|
|
output up_ch_enb_18,
|
|
output [11:0] up_ch_addr_18,
|
|
output up_ch_wr_18,
|
|
output [15:0] up_ch_wdata_18,
|
|
input [15:0] up_ch_rdata_18,
|
|
input up_ch_ready_18,
|
|
|
|
output up_es_enb_19,
|
|
output [11:0] up_es_addr_19,
|
|
output up_es_wr_19,
|
|
output up_es_reset_19,
|
|
output [15:0] up_es_wdata_19,
|
|
input [15:0] up_es_rdata_19,
|
|
input up_es_ready_19,
|
|
|
|
input up_ch_pll_locked_19,
|
|
output up_ch_rst_19,
|
|
output up_ch_user_ready_19,
|
|
input up_ch_rst_done_19,
|
|
output up_ch_prbsforceerr_19,
|
|
output [ 3:0] up_ch_prbssel_19,
|
|
output up_ch_prbscntreset_19,
|
|
input up_ch_prbserr_19,
|
|
input up_ch_prbslocked_19,
|
|
input [ 1:0] up_ch_bufstatus_19,
|
|
output up_ch_bufstatus_rst_19,
|
|
output up_ch_lpm_dfe_n_19,
|
|
output [ 2:0] up_ch_rate_19,
|
|
output [ 1:0] up_ch_sys_clk_sel_19,
|
|
output [ 2:0] up_ch_out_clk_sel_19,
|
|
output [ 4:0] up_ch_tx_diffctrl_19,
|
|
output [ 4:0] up_ch_tx_postcursor_19,
|
|
output [ 4:0] up_ch_tx_precursor_19,
|
|
output up_ch_enb_19,
|
|
output [11:0] up_ch_addr_19,
|
|
output up_ch_wr_19,
|
|
output [15:0] up_ch_wdata_19,
|
|
input [15:0] up_ch_rdata_19,
|
|
input up_ch_ready_19,
|
|
|
|
output up_cm_enb_20,
|
|
output [11:0] up_cm_addr_20,
|
|
output up_cm_wr_20,
|
|
output [15:0] up_cm_wdata_20,
|
|
input [15:0] up_cm_rdata_20,
|
|
input up_cm_ready_20,
|
|
|
|
output up_es_enb_20,
|
|
output [11:0] up_es_addr_20,
|
|
output up_es_wr_20,
|
|
output up_es_reset_20,
|
|
output [15:0] up_es_wdata_20,
|
|
input [15:0] up_es_rdata_20,
|
|
input up_es_ready_20,
|
|
|
|
input up_ch_pll_locked_20,
|
|
output up_ch_rst_20,
|
|
output up_ch_user_ready_20,
|
|
input up_ch_rst_done_20,
|
|
output up_ch_prbsforceerr_20,
|
|
output [ 3:0] up_ch_prbssel_20,
|
|
output up_ch_prbscntreset_20,
|
|
input up_ch_prbserr_20,
|
|
input up_ch_prbslocked_20,
|
|
input [ 1:0] up_ch_bufstatus_20,
|
|
output up_ch_bufstatus_rst_20,
|
|
output up_ch_lpm_dfe_n_20,
|
|
output [ 2:0] up_ch_rate_20,
|
|
output [ 1:0] up_ch_sys_clk_sel_20,
|
|
output [ 2:0] up_ch_out_clk_sel_20,
|
|
output [ 4:0] up_ch_tx_diffctrl_20,
|
|
output [ 4:0] up_ch_tx_postcursor_20,
|
|
output [ 4:0] up_ch_tx_precursor_20,
|
|
output up_ch_enb_20,
|
|
output [11:0] up_ch_addr_20,
|
|
output up_ch_wr_20,
|
|
output [15:0] up_ch_wdata_20,
|
|
input [15:0] up_ch_rdata_20,
|
|
input up_ch_ready_20,
|
|
|
|
output up_es_enb_21,
|
|
output [11:0] up_es_addr_21,
|
|
output up_es_wr_21,
|
|
output up_es_reset_21,
|
|
output [15:0] up_es_wdata_21,
|
|
input [15:0] up_es_rdata_21,
|
|
input up_es_ready_21,
|
|
|
|
input up_ch_pll_locked_21,
|
|
output up_ch_rst_21,
|
|
output up_ch_user_ready_21,
|
|
input up_ch_rst_done_21,
|
|
output up_ch_prbsforceerr_21,
|
|
output [ 3:0] up_ch_prbssel_21,
|
|
output up_ch_prbscntreset_21,
|
|
input up_ch_prbserr_21,
|
|
input up_ch_prbslocked_21,
|
|
input [ 1:0] up_ch_bufstatus_21,
|
|
output up_ch_bufstatus_rst_21,
|
|
output up_ch_lpm_dfe_n_21,
|
|
output [ 2:0] up_ch_rate_21,
|
|
output [ 1:0] up_ch_sys_clk_sel_21,
|
|
output [ 2:0] up_ch_out_clk_sel_21,
|
|
output [ 4:0] up_ch_tx_diffctrl_21,
|
|
output [ 4:0] up_ch_tx_postcursor_21,
|
|
output [ 4:0] up_ch_tx_precursor_21,
|
|
output up_ch_enb_21,
|
|
output [11:0] up_ch_addr_21,
|
|
output up_ch_wr_21,
|
|
output [15:0] up_ch_wdata_21,
|
|
input [15:0] up_ch_rdata_21,
|
|
input up_ch_ready_21,
|
|
|
|
output up_es_enb_22,
|
|
output [11:0] up_es_addr_22,
|
|
output up_es_wr_22,
|
|
output up_es_reset_22,
|
|
output [15:0] up_es_wdata_22,
|
|
input [15:0] up_es_rdata_22,
|
|
input up_es_ready_22,
|
|
|
|
input up_ch_pll_locked_22,
|
|
output up_ch_rst_22,
|
|
output up_ch_user_ready_22,
|
|
input up_ch_rst_done_22,
|
|
output up_ch_prbsforceerr_22,
|
|
output [ 3:0] up_ch_prbssel_22,
|
|
output up_ch_prbscntreset_22,
|
|
input up_ch_prbserr_22,
|
|
input up_ch_prbslocked_22,
|
|
input [ 1:0] up_ch_bufstatus_22,
|
|
output up_ch_bufstatus_rst_22,
|
|
output up_ch_lpm_dfe_n_22,
|
|
output [ 2:0] up_ch_rate_22,
|
|
output [ 1:0] up_ch_sys_clk_sel_22,
|
|
output [ 2:0] up_ch_out_clk_sel_22,
|
|
output [ 4:0] up_ch_tx_diffctrl_22,
|
|
output [ 4:0] up_ch_tx_postcursor_22,
|
|
output [ 4:0] up_ch_tx_precursor_22,
|
|
output up_ch_enb_22,
|
|
output [11:0] up_ch_addr_22,
|
|
output up_ch_wr_22,
|
|
output [15:0] up_ch_wdata_22,
|
|
input [15:0] up_ch_rdata_22,
|
|
input up_ch_ready_22,
|
|
|
|
output up_es_enb_23,
|
|
output [11:0] up_es_addr_23,
|
|
output up_es_wr_23,
|
|
output up_es_reset_23,
|
|
output [15:0] up_es_wdata_23,
|
|
input [15:0] up_es_rdata_23,
|
|
input up_es_ready_23,
|
|
|
|
input up_ch_pll_locked_23,
|
|
output up_ch_rst_23,
|
|
output up_ch_user_ready_23,
|
|
input up_ch_rst_done_23,
|
|
output up_ch_prbsforceerr_23,
|
|
output [ 3:0] up_ch_prbssel_23,
|
|
output up_ch_prbscntreset_23,
|
|
input up_ch_prbserr_23,
|
|
input up_ch_prbslocked_23,
|
|
input [ 1:0] up_ch_bufstatus_23,
|
|
output up_ch_bufstatus_rst_23,
|
|
output up_ch_lpm_dfe_n_23,
|
|
output [ 2:0] up_ch_rate_23,
|
|
output [ 1:0] up_ch_sys_clk_sel_23,
|
|
output [ 2:0] up_ch_out_clk_sel_23,
|
|
output [ 4:0] up_ch_tx_diffctrl_23,
|
|
output [ 4:0] up_ch_tx_postcursor_23,
|
|
output [ 4:0] up_ch_tx_precursor_23,
|
|
output up_ch_enb_23,
|
|
output [11:0] up_ch_addr_23,
|
|
output up_ch_wr_23,
|
|
output [15:0] up_ch_wdata_23,
|
|
input [15:0] up_ch_rdata_23,
|
|
input up_ch_ready_23,
|
|
|
|
output up_cm_enb_24,
|
|
output [11:0] up_cm_addr_24,
|
|
output up_cm_wr_24,
|
|
output [15:0] up_cm_wdata_24,
|
|
input [15:0] up_cm_rdata_24,
|
|
input up_cm_ready_24,
|
|
|
|
output up_es_enb_24,
|
|
output [11:0] up_es_addr_24,
|
|
output up_es_wr_24,
|
|
output up_es_reset_24,
|
|
output [15:0] up_es_wdata_24,
|
|
input [15:0] up_es_rdata_24,
|
|
input up_es_ready_24,
|
|
|
|
input up_ch_pll_locked_24,
|
|
output up_ch_rst_24,
|
|
output up_ch_user_ready_24,
|
|
input up_ch_rst_done_24,
|
|
output up_ch_prbsforceerr_24,
|
|
output [ 3:0] up_ch_prbssel_24,
|
|
output up_ch_prbscntreset_24,
|
|
input up_ch_prbserr_24,
|
|
input up_ch_prbslocked_24,
|
|
input [ 1:0] up_ch_bufstatus_24,
|
|
output up_ch_bufstatus_rst_24,
|
|
output up_ch_lpm_dfe_n_24,
|
|
output [ 2:0] up_ch_rate_24,
|
|
output [ 1:0] up_ch_sys_clk_sel_24,
|
|
output [ 2:0] up_ch_out_clk_sel_24,
|
|
output [ 4:0] up_ch_tx_diffctrl_24,
|
|
output [ 4:0] up_ch_tx_postcursor_24,
|
|
output [ 4:0] up_ch_tx_precursor_24,
|
|
output up_ch_enb_24,
|
|
output [11:0] up_ch_addr_24,
|
|
output up_ch_wr_24,
|
|
output [15:0] up_ch_wdata_24,
|
|
input [15:0] up_ch_rdata_24,
|
|
input up_ch_ready_24,
|
|
|
|
output up_es_enb_25,
|
|
output [11:0] up_es_addr_25,
|
|
output up_es_wr_25,
|
|
output up_es_reset_25,
|
|
output [15:0] up_es_wdata_25,
|
|
input [15:0] up_es_rdata_25,
|
|
input up_es_ready_25,
|
|
|
|
input up_ch_pll_locked_25,
|
|
output up_ch_rst_25,
|
|
output up_ch_user_ready_25,
|
|
input up_ch_rst_done_25,
|
|
output up_ch_prbsforceerr_25,
|
|
output [ 3:0] up_ch_prbssel_25,
|
|
output up_ch_prbscntreset_25,
|
|
input up_ch_prbserr_25,
|
|
input up_ch_prbslocked_25,
|
|
input [ 1:0] up_ch_bufstatus_25,
|
|
output up_ch_bufstatus_rst_25,
|
|
output up_ch_lpm_dfe_n_25,
|
|
output [ 2:0] up_ch_rate_25,
|
|
output [ 1:0] up_ch_sys_clk_sel_25,
|
|
output [ 2:0] up_ch_out_clk_sel_25,
|
|
output [ 4:0] up_ch_tx_diffctrl_25,
|
|
output [ 4:0] up_ch_tx_postcursor_25,
|
|
output [ 4:0] up_ch_tx_precursor_25,
|
|
output up_ch_enb_25,
|
|
output [11:0] up_ch_addr_25,
|
|
output up_ch_wr_25,
|
|
output [15:0] up_ch_wdata_25,
|
|
input [15:0] up_ch_rdata_25,
|
|
input up_ch_ready_25,
|
|
|
|
output up_es_enb_26,
|
|
output [11:0] up_es_addr_26,
|
|
output up_es_wr_26,
|
|
output up_es_reset_26,
|
|
output [15:0] up_es_wdata_26,
|
|
input [15:0] up_es_rdata_26,
|
|
input up_es_ready_26,
|
|
|
|
input up_ch_pll_locked_26,
|
|
output up_ch_rst_26,
|
|
output up_ch_user_ready_26,
|
|
input up_ch_rst_done_26,
|
|
output up_ch_prbsforceerr_26,
|
|
output [ 3:0] up_ch_prbssel_26,
|
|
output up_ch_prbscntreset_26,
|
|
input up_ch_prbserr_26,
|
|
input up_ch_prbslocked_26,
|
|
input [ 1:0] up_ch_bufstatus_26,
|
|
output up_ch_bufstatus_rst_26,
|
|
output up_ch_lpm_dfe_n_26,
|
|
output [ 2:0] up_ch_rate_26,
|
|
output [ 1:0] up_ch_sys_clk_sel_26,
|
|
output [ 2:0] up_ch_out_clk_sel_26,
|
|
output [ 4:0] up_ch_tx_diffctrl_26,
|
|
output [ 4:0] up_ch_tx_postcursor_26,
|
|
output [ 4:0] up_ch_tx_precursor_26,
|
|
output up_ch_enb_26,
|
|
output [11:0] up_ch_addr_26,
|
|
output up_ch_wr_26,
|
|
output [15:0] up_ch_wdata_26,
|
|
input [15:0] up_ch_rdata_26,
|
|
input up_ch_ready_26,
|
|
|
|
output up_es_enb_27,
|
|
output [11:0] up_es_addr_27,
|
|
output up_es_wr_27,
|
|
output up_es_reset_27,
|
|
output [15:0] up_es_wdata_27,
|
|
input [15:0] up_es_rdata_27,
|
|
input up_es_ready_27,
|
|
|
|
input up_ch_pll_locked_27,
|
|
output up_ch_rst_27,
|
|
output up_ch_user_ready_27,
|
|
input up_ch_rst_done_27,
|
|
output up_ch_prbsforceerr_27,
|
|
output [ 3:0] up_ch_prbssel_27,
|
|
output up_ch_prbscntreset_27,
|
|
input up_ch_prbserr_27,
|
|
input up_ch_prbslocked_27,
|
|
input [ 1:0] up_ch_bufstatus_27,
|
|
output up_ch_bufstatus_rst_27,
|
|
output up_ch_lpm_dfe_n_27,
|
|
output [ 2:0] up_ch_rate_27,
|
|
output [ 1:0] up_ch_sys_clk_sel_27,
|
|
output [ 2:0] up_ch_out_clk_sel_27,
|
|
output [ 4:0] up_ch_tx_diffctrl_27,
|
|
output [ 4:0] up_ch_tx_postcursor_27,
|
|
output [ 4:0] up_ch_tx_precursor_27,
|
|
output up_ch_enb_27,
|
|
output [11:0] up_ch_addr_27,
|
|
output up_ch_wr_27,
|
|
output [15:0] up_ch_wdata_27,
|
|
input [15:0] up_ch_rdata_27,
|
|
input up_ch_ready_27,
|
|
|
|
output up_cm_enb_28,
|
|
output [11:0] up_cm_addr_28,
|
|
output up_cm_wr_28,
|
|
output [15:0] up_cm_wdata_28,
|
|
input [15:0] up_cm_rdata_28,
|
|
input up_cm_ready_28,
|
|
|
|
output up_es_enb_28,
|
|
output [11:0] up_es_addr_28,
|
|
output up_es_wr_28,
|
|
output up_es_reset_28,
|
|
output [15:0] up_es_wdata_28,
|
|
input [15:0] up_es_rdata_28,
|
|
input up_es_ready_28,
|
|
|
|
input up_ch_pll_locked_28,
|
|
output up_ch_rst_28,
|
|
output up_ch_user_ready_28,
|
|
input up_ch_rst_done_28,
|
|
output up_ch_prbsforceerr_28,
|
|
output [ 3:0] up_ch_prbssel_28,
|
|
output up_ch_prbscntreset_28,
|
|
input up_ch_prbserr_28,
|
|
input up_ch_prbslocked_28,
|
|
input [ 1:0] up_ch_bufstatus_28,
|
|
output up_ch_bufstatus_rst_28,
|
|
output up_ch_lpm_dfe_n_28,
|
|
output [ 2:0] up_ch_rate_28,
|
|
output [ 1:0] up_ch_sys_clk_sel_28,
|
|
output [ 2:0] up_ch_out_clk_sel_28,
|
|
output [ 4:0] up_ch_tx_diffctrl_28,
|
|
output [ 4:0] up_ch_tx_postcursor_28,
|
|
output [ 4:0] up_ch_tx_precursor_28,
|
|
output up_ch_enb_28,
|
|
output [11:0] up_ch_addr_28,
|
|
output up_ch_wr_28,
|
|
output [15:0] up_ch_wdata_28,
|
|
input [15:0] up_ch_rdata_28,
|
|
input up_ch_ready_28,
|
|
|
|
output up_es_enb_29,
|
|
output [11:0] up_es_addr_29,
|
|
output up_es_wr_29,
|
|
output up_es_reset_29,
|
|
output [15:0] up_es_wdata_29,
|
|
input [15:0] up_es_rdata_29,
|
|
input up_es_ready_29,
|
|
|
|
input up_ch_pll_locked_29,
|
|
output up_ch_rst_29,
|
|
output up_ch_user_ready_29,
|
|
input up_ch_rst_done_29,
|
|
output up_ch_prbsforceerr_29,
|
|
output [ 3:0] up_ch_prbssel_29,
|
|
output up_ch_prbscntreset_29,
|
|
input up_ch_prbserr_29,
|
|
input up_ch_prbslocked_29,
|
|
input [ 1:0] up_ch_bufstatus_29,
|
|
output up_ch_bufstatus_rst_29,
|
|
output up_ch_lpm_dfe_n_29,
|
|
output [ 2:0] up_ch_rate_29,
|
|
output [ 1:0] up_ch_sys_clk_sel_29,
|
|
output [ 2:0] up_ch_out_clk_sel_29,
|
|
output [ 4:0] up_ch_tx_diffctrl_29,
|
|
output [ 4:0] up_ch_tx_postcursor_29,
|
|
output [ 4:0] up_ch_tx_precursor_29,
|
|
output up_ch_enb_29,
|
|
output [11:0] up_ch_addr_29,
|
|
output up_ch_wr_29,
|
|
output [15:0] up_ch_wdata_29,
|
|
input [15:0] up_ch_rdata_29,
|
|
input up_ch_ready_29,
|
|
|
|
output up_es_enb_30,
|
|
output [11:0] up_es_addr_30,
|
|
output up_es_wr_30,
|
|
output up_es_reset_30,
|
|
output [15:0] up_es_wdata_30,
|
|
input [15:0] up_es_rdata_30,
|
|
input up_es_ready_30,
|
|
|
|
input up_ch_pll_locked_30,
|
|
output up_ch_rst_30,
|
|
output up_ch_user_ready_30,
|
|
input up_ch_rst_done_30,
|
|
output up_ch_prbsforceerr_30,
|
|
output [ 3:0] up_ch_prbssel_30,
|
|
output up_ch_prbscntreset_30,
|
|
input up_ch_prbserr_30,
|
|
input up_ch_prbslocked_30,
|
|
input [ 1:0] up_ch_bufstatus_30,
|
|
output up_ch_bufstatus_rst_30,
|
|
output up_ch_lpm_dfe_n_30,
|
|
output [ 2:0] up_ch_rate_30,
|
|
output [ 1:0] up_ch_sys_clk_sel_30,
|
|
output [ 2:0] up_ch_out_clk_sel_30,
|
|
output [ 4:0] up_ch_tx_diffctrl_30,
|
|
output [ 4:0] up_ch_tx_postcursor_30,
|
|
output [ 4:0] up_ch_tx_precursor_30,
|
|
output up_ch_enb_30,
|
|
output [11:0] up_ch_addr_30,
|
|
output up_ch_wr_30,
|
|
output [15:0] up_ch_wdata_30,
|
|
input [15:0] up_ch_rdata_30,
|
|
input up_ch_ready_30,
|
|
|
|
output up_es_enb_31,
|
|
output [11:0] up_es_addr_31,
|
|
output up_es_wr_31,
|
|
output up_es_reset_31,
|
|
output [15:0] up_es_wdata_31,
|
|
input [15:0] up_es_rdata_31,
|
|
input up_es_ready_31,
|
|
|
|
input up_ch_pll_locked_31,
|
|
output up_ch_rst_31,
|
|
output up_ch_user_ready_31,
|
|
input up_ch_rst_done_31,
|
|
output up_ch_prbsforceerr_31,
|
|
output [ 3:0] up_ch_prbssel_31,
|
|
output up_ch_prbscntreset_31,
|
|
input up_ch_prbserr_31,
|
|
input up_ch_prbslocked_31,
|
|
input [ 1:0] up_ch_bufstatus_31,
|
|
output up_ch_bufstatus_rst_31,
|
|
output up_ch_lpm_dfe_n_31,
|
|
output [ 2:0] up_ch_rate_31,
|
|
output [ 1:0] up_ch_sys_clk_sel_31,
|
|
output [ 2:0] up_ch_out_clk_sel_31,
|
|
output [ 4:0] up_ch_tx_diffctrl_31,
|
|
output [ 4:0] up_ch_tx_postcursor_31,
|
|
output [ 4:0] up_ch_tx_precursor_31,
|
|
output up_ch_enb_31,
|
|
output [11:0] up_ch_addr_31,
|
|
output up_ch_wr_31,
|
|
output [15:0] up_ch_wdata_31,
|
|
input [15:0] up_ch_rdata_31,
|
|
input up_ch_ready_31,
|
|
|
|
input s_axi_aclk,
|
|
input s_axi_aresetn,
|
|
output up_status,
|
|
output up_pll_rst,
|
|
|
|
input s_axi_awvalid,
|
|
input [15:0] s_axi_awaddr,
|
|
input [ 2:0] s_axi_awprot,
|
|
output s_axi_awready,
|
|
input s_axi_wvalid,
|
|
input [31:0] s_axi_wdata,
|
|
input [ 3:0] s_axi_wstrb,
|
|
output s_axi_wready,
|
|
output s_axi_bvalid,
|
|
output [ 1:0] s_axi_bresp,
|
|
input s_axi_bready,
|
|
input s_axi_arvalid,
|
|
input [15:0] s_axi_araddr,
|
|
input [ 2:0] s_axi_arprot,
|
|
output s_axi_arready,
|
|
output s_axi_rvalid,
|
|
output [ 1:0] s_axi_rresp,
|
|
output [31:0] s_axi_rdata,
|
|
input s_axi_rready,
|
|
|
|
output m_axi_awvalid,
|
|
output [31:0] m_axi_awaddr,
|
|
output [ 2:0] m_axi_awprot,
|
|
input m_axi_awready,
|
|
output m_axi_wvalid,
|
|
output [31:0] m_axi_wdata,
|
|
output [ 3:0] m_axi_wstrb,
|
|
input m_axi_wready,
|
|
input m_axi_bvalid,
|
|
input [ 1:0] m_axi_bresp,
|
|
output m_axi_bready,
|
|
output m_axi_arvalid,
|
|
output [31:0] m_axi_araddr,
|
|
output [ 2:0] m_axi_arprot,
|
|
input m_axi_arready,
|
|
input m_axi_rvalid,
|
|
input [31:0] m_axi_rdata,
|
|
input [ 1:0] m_axi_rresp,
|
|
output m_axi_rready
|
|
);
|
|
|
|
// internal signals
|
|
|
|
wire [ 7:0] up_cm_sel;
|
|
wire up_cm_enb;
|
|
wire [11:0] up_cm_addr;
|
|
wire up_cm_wr;
|
|
wire [15:0] up_cm_wdata;
|
|
wire [15:0] up_cm_rdata_0_s;
|
|
wire up_cm_ready_0_s;
|
|
wire [15:0] up_cm_rdata_4_s;
|
|
wire up_cm_ready_4_s;
|
|
wire [15:0] up_cm_rdata_8_s;
|
|
wire up_cm_ready_8_s;
|
|
wire [15:0] up_cm_rdata_12_s;
|
|
wire up_cm_ready_12_s;
|
|
wire [15:0] up_cm_rdata_16_s;
|
|
wire up_cm_ready_16_s;
|
|
wire [15:0] up_cm_rdata_20_s;
|
|
wire up_cm_ready_20_s;
|
|
wire [15:0] up_cm_rdata_24_s;
|
|
wire up_cm_ready_24_s;
|
|
wire [15:0] up_cm_rdata_28_s;
|
|
wire up_cm_ready_28_s;
|
|
wire [ 7:0] up_es_sel;
|
|
wire up_es_enb;
|
|
wire [11:0] up_es_addr;
|
|
wire up_es_wr;
|
|
wire [15:0] up_es_wdata;
|
|
wire [15:0] up_es_rdata_0_s;
|
|
wire up_es_ready_0_s;
|
|
wire [15:0] up_es_rdata_1_s;
|
|
wire up_es_ready_1_s;
|
|
wire [15:0] up_es_rdata_2_s;
|
|
wire up_es_ready_2_s;
|
|
wire [15:0] up_es_rdata_3_s;
|
|
wire up_es_ready_3_s;
|
|
wire [15:0] up_es_rdata_4_s;
|
|
wire up_es_ready_4_s;
|
|
wire [15:0] up_es_rdata_5_s;
|
|
wire up_es_ready_5_s;
|
|
wire [15:0] up_es_rdata_6_s;
|
|
wire up_es_ready_6_s;
|
|
wire [15:0] up_es_rdata_7_s;
|
|
wire up_es_ready_7_s;
|
|
wire [15:0] up_es_rdata_8_s;
|
|
wire up_es_ready_8_s;
|
|
wire [15:0] up_es_rdata_9_s;
|
|
wire up_es_ready_9_s;
|
|
wire [15:0] up_es_rdata_10_s;
|
|
wire up_es_ready_10_s;
|
|
wire [15:0] up_es_rdata_11_s;
|
|
wire up_es_ready_11_s;
|
|
wire [15:0] up_es_rdata_12_s;
|
|
wire up_es_ready_12_s;
|
|
wire [15:0] up_es_rdata_13_s;
|
|
wire up_es_ready_13_s;
|
|
wire [15:0] up_es_rdata_14_s;
|
|
wire up_es_ready_14_s;
|
|
wire [15:0] up_es_rdata_15_s;
|
|
wire up_es_ready_15_s;
|
|
wire [15:0] up_es_rdata_16_s;
|
|
wire up_es_ready_16_s;
|
|
wire [15:0] up_es_rdata_17_s;
|
|
wire up_es_ready_17_s;
|
|
wire [15:0] up_es_rdata_18_s;
|
|
wire up_es_ready_18_s;
|
|
wire [15:0] up_es_rdata_19_s;
|
|
wire up_es_ready_19_s;
|
|
wire [15:0] up_es_rdata_20_s;
|
|
wire up_es_ready_20_s;
|
|
wire [15:0] up_es_rdata_21_s;
|
|
wire up_es_ready_21_s;
|
|
wire [15:0] up_es_rdata_22_s;
|
|
wire up_es_ready_22_s;
|
|
wire [15:0] up_es_rdata_23_s;
|
|
wire up_es_ready_23_s;
|
|
wire [15:0] up_es_rdata_24_s;
|
|
wire up_es_ready_24_s;
|
|
wire [15:0] up_es_rdata_25_s;
|
|
wire up_es_ready_25_s;
|
|
wire [15:0] up_es_rdata_26_s;
|
|
wire up_es_ready_26_s;
|
|
wire [15:0] up_es_rdata_27_s;
|
|
wire up_es_ready_27_s;
|
|
wire [15:0] up_es_rdata_28_s;
|
|
wire up_es_ready_28_s;
|
|
wire [15:0] up_es_rdata_29_s;
|
|
wire up_es_ready_29_s;
|
|
wire [15:0] up_es_rdata_30_s;
|
|
wire up_es_ready_30_s;
|
|
wire [15:0] up_es_rdata_31_s;
|
|
wire up_es_ready_31_s;
|
|
wire up_ch_rst;
|
|
wire up_ch_user_ready;
|
|
wire up_ch_lpm_dfe_n;
|
|
wire [ 2:0] up_ch_rate;
|
|
wire [ 1:0] up_ch_sys_clk_sel;
|
|
wire [ 2:0] up_ch_out_clk_sel;
|
|
wire [ 4:0] up_ch_tx_diffctrl;
|
|
wire [ 4:0] up_ch_tx_postcursor;
|
|
wire [ 4:0] up_ch_tx_precursor;
|
|
wire up_ch_prbsforceerr;
|
|
wire [ 3:0] up_ch_prbssel;
|
|
wire up_ch_prbscntreset;
|
|
wire up_ch_bufstatus_rst;
|
|
wire up_ch_pll_locked_0_s;
|
|
wire up_ch_rst_done_0_s;
|
|
wire up_ch_prbserr_0_s;
|
|
wire up_ch_prbslocked_0_s;
|
|
wire [ 1:0] up_ch_bufstatus_0_s;
|
|
wire up_ch_pll_locked_1_s;
|
|
wire up_ch_rst_done_1_s;
|
|
wire up_ch_prbserr_1_s;
|
|
wire up_ch_prbslocked_1_s;
|
|
wire [ 1:0] up_ch_bufstatus_1_s;
|
|
wire up_ch_pll_locked_2_s;
|
|
wire up_ch_rst_done_2_s;
|
|
wire up_ch_prbserr_2_s;
|
|
wire up_ch_prbslocked_2_s;
|
|
wire [ 1:0] up_ch_bufstatus_2_s;
|
|
wire up_ch_pll_locked_3_s;
|
|
wire up_ch_rst_done_3_s;
|
|
wire up_ch_prbserr_3_s;
|
|
wire up_ch_prbslocked_3_s;
|
|
wire [ 1:0] up_ch_bufstatus_3_s;
|
|
wire up_ch_pll_locked_4_s;
|
|
wire up_ch_rst_done_4_s;
|
|
wire up_ch_prbserr_4_s;
|
|
wire up_ch_prbslocked_4_s;
|
|
wire [ 1:0] up_ch_bufstatus_4_s;
|
|
wire up_ch_pll_locked_5_s;
|
|
wire up_ch_rst_done_5_s;
|
|
wire up_ch_prbserr_5_s;
|
|
wire up_ch_prbslocked_5_s;
|
|
wire [ 1:0] up_ch_bufstatus_5_s;
|
|
wire up_ch_pll_locked_6_s;
|
|
wire up_ch_rst_done_6_s;
|
|
wire up_ch_prbserr_6_s;
|
|
wire up_ch_prbslocked_6_s;
|
|
wire [ 1:0] up_ch_bufstatus_6_s;
|
|
wire up_ch_pll_locked_7_s;
|
|
wire up_ch_rst_done_7_s;
|
|
wire up_ch_prbserr_7_s;
|
|
wire up_ch_prbslocked_7_s;
|
|
wire [ 1:0] up_ch_bufstatus_7_s;
|
|
wire up_ch_pll_locked_8_s;
|
|
wire up_ch_rst_done_8_s;
|
|
wire up_ch_prbserr_8_s;
|
|
wire up_ch_prbslocked_8_s;
|
|
wire [ 1:0] up_ch_bufstatus_8_s;
|
|
wire up_ch_pll_locked_9_s;
|
|
wire up_ch_rst_done_9_s;
|
|
wire up_ch_prbserr_9_s;
|
|
wire up_ch_prbslocked_9_s;
|
|
wire [ 1:0] up_ch_bufstatus_9_s;
|
|
wire up_ch_pll_locked_10_s;
|
|
wire up_ch_rst_done_10_s;
|
|
wire up_ch_prbserr_10_s;
|
|
wire up_ch_prbslocked_10_s;
|
|
wire [ 1:0] up_ch_bufstatus_10_s;
|
|
wire up_ch_pll_locked_11_s;
|
|
wire up_ch_rst_done_11_s;
|
|
wire up_ch_prbserr_11_s;
|
|
wire up_ch_prbslocked_11_s;
|
|
wire [ 1:0] up_ch_bufstatus_11_s;
|
|
wire up_ch_pll_locked_12_s;
|
|
wire up_ch_rst_done_12_s;
|
|
wire up_ch_prbserr_12_s;
|
|
wire up_ch_prbslocked_12_s;
|
|
wire [ 1:0] up_ch_bufstatus_12_s;
|
|
wire up_ch_pll_locked_13_s;
|
|
wire up_ch_rst_done_13_s;
|
|
wire up_ch_prbserr_13_s;
|
|
wire up_ch_prbslocked_13_s;
|
|
wire [ 1:0] up_ch_bufstatus_13_s;
|
|
wire up_ch_pll_locked_14_s;
|
|
wire up_ch_rst_done_14_s;
|
|
wire up_ch_prbserr_14_s;
|
|
wire up_ch_prbslocked_14_s;
|
|
wire [ 1:0] up_ch_bufstatus_14_s;
|
|
wire up_ch_pll_locked_15_s;
|
|
wire up_ch_rst_done_15_s;
|
|
wire up_ch_prbserr_15_s;
|
|
wire up_ch_prbslocked_15_s;
|
|
wire [ 1:0] up_ch_bufstatus_15_s;
|
|
wire up_ch_pll_locked_16_s;
|
|
wire up_ch_rst_done_16_s;
|
|
wire up_ch_prbserr_16_s;
|
|
wire up_ch_prbslocked_16_s;
|
|
wire [ 1:0] up_ch_bufstatus_16_s;
|
|
wire up_ch_pll_locked_17_s;
|
|
wire up_ch_rst_done_17_s;
|
|
wire up_ch_prbserr_17_s;
|
|
wire up_ch_prbslocked_17_s;
|
|
wire [ 1:0] up_ch_bufstatus_17_s;
|
|
wire up_ch_pll_locked_18_s;
|
|
wire up_ch_rst_done_18_s;
|
|
wire up_ch_prbserr_18_s;
|
|
wire up_ch_prbslocked_18_s;
|
|
wire [ 1:0] up_ch_bufstatus_18_s;
|
|
wire up_ch_pll_locked_19_s;
|
|
wire up_ch_rst_done_19_s;
|
|
wire up_ch_prbserr_19_s;
|
|
wire up_ch_prbslocked_19_s;
|
|
wire [ 1:0] up_ch_bufstatus_19_s;
|
|
wire up_ch_pll_locked_20_s;
|
|
wire up_ch_rst_done_20_s;
|
|
wire up_ch_prbserr_20_s;
|
|
wire up_ch_prbslocked_20_s;
|
|
wire [ 1:0] up_ch_bufstatus_20_s;
|
|
wire up_ch_pll_locked_21_s;
|
|
wire up_ch_rst_done_21_s;
|
|
wire up_ch_prbserr_21_s;
|
|
wire up_ch_prbslocked_21_s;
|
|
wire [ 1:0] up_ch_bufstatus_21_s;
|
|
wire up_ch_pll_locked_22_s;
|
|
wire up_ch_rst_done_22_s;
|
|
wire up_ch_prbserr_22_s;
|
|
wire up_ch_prbslocked_22_s;
|
|
wire [ 1:0] up_ch_bufstatus_22_s;
|
|
wire up_ch_pll_locked_23_s;
|
|
wire up_ch_rst_done_23_s;
|
|
wire up_ch_prbserr_23_s;
|
|
wire up_ch_prbslocked_23_s;
|
|
wire [ 1:0] up_ch_bufstatus_23_s;
|
|
wire up_ch_pll_locked_24_s;
|
|
wire up_ch_rst_done_24_s;
|
|
wire up_ch_prbserr_24_s;
|
|
wire up_ch_prbslocked_24_s;
|
|
wire [ 1:0] up_ch_bufstatus_24_s;
|
|
wire up_ch_pll_locked_25_s;
|
|
wire up_ch_rst_done_25_s;
|
|
wire up_ch_prbserr_25_s;
|
|
wire up_ch_prbslocked_25_s;
|
|
wire [ 1:0] up_ch_bufstatus_25_s;
|
|
wire up_ch_pll_locked_26_s;
|
|
wire up_ch_rst_done_26_s;
|
|
wire up_ch_prbserr_26_s;
|
|
wire up_ch_prbslocked_26_s;
|
|
wire [ 1:0] up_ch_bufstatus_26_s;
|
|
wire up_ch_pll_locked_27_s;
|
|
wire up_ch_rst_done_27_s;
|
|
wire up_ch_prbserr_27_s;
|
|
wire up_ch_prbslocked_27_s;
|
|
wire [ 1:0] up_ch_bufstatus_27_s;
|
|
wire up_ch_pll_locked_28_s;
|
|
wire up_ch_rst_done_28_s;
|
|
wire up_ch_prbserr_28_s;
|
|
wire up_ch_prbslocked_28_s;
|
|
wire [ 1:0] up_ch_bufstatus_28_s;
|
|
wire up_ch_pll_locked_29_s;
|
|
wire up_ch_rst_done_29_s;
|
|
wire up_ch_prbserr_29_s;
|
|
wire up_ch_prbslocked_29_s;
|
|
wire [ 1:0] up_ch_bufstatus_29_s;
|
|
wire up_ch_pll_locked_30_s;
|
|
wire up_ch_rst_done_30_s;
|
|
wire up_ch_prbserr_30_s;
|
|
wire up_ch_prbslocked_30_s;
|
|
wire [ 1:0] up_ch_bufstatus_30_s;
|
|
wire up_ch_pll_locked_31_s;
|
|
wire up_ch_rst_done_31_s;
|
|
wire up_ch_prbserr_31_s;
|
|
wire up_ch_prbslocked_31_s;
|
|
wire [ 1:0] up_ch_bufstatus_31_s;
|
|
wire [ 7:0] up_ch_sel;
|
|
wire up_ch_enb;
|
|
wire [11:0] up_ch_addr;
|
|
wire up_ch_wr;
|
|
wire [15:0] up_ch_wdata;
|
|
wire [15:0] up_ch_rdata_0_s;
|
|
wire up_ch_ready_0_s;
|
|
wire [15:0] up_ch_rdata_1_s;
|
|
wire up_ch_ready_1_s;
|
|
wire [15:0] up_ch_rdata_2_s;
|
|
wire up_ch_ready_2_s;
|
|
wire [15:0] up_ch_rdata_3_s;
|
|
wire up_ch_ready_3_s;
|
|
wire [15:0] up_ch_rdata_4_s;
|
|
wire up_ch_ready_4_s;
|
|
wire [15:0] up_ch_rdata_5_s;
|
|
wire up_ch_ready_5_s;
|
|
wire [15:0] up_ch_rdata_6_s;
|
|
wire up_ch_ready_6_s;
|
|
wire [15:0] up_ch_rdata_7_s;
|
|
wire up_ch_ready_7_s;
|
|
wire [15:0] up_ch_rdata_8_s;
|
|
wire up_ch_ready_8_s;
|
|
wire [15:0] up_ch_rdata_9_s;
|
|
wire up_ch_ready_9_s;
|
|
wire [15:0] up_ch_rdata_10_s;
|
|
wire up_ch_ready_10_s;
|
|
wire [15:0] up_ch_rdata_11_s;
|
|
wire up_ch_ready_11_s;
|
|
wire [15:0] up_ch_rdata_12_s;
|
|
wire up_ch_ready_12_s;
|
|
wire [15:0] up_ch_rdata_13_s;
|
|
wire up_ch_ready_13_s;
|
|
wire [15:0] up_ch_rdata_14_s;
|
|
wire up_ch_ready_14_s;
|
|
wire [15:0] up_ch_rdata_15_s;
|
|
wire up_ch_ready_15_s;
|
|
wire [15:0] up_ch_rdata_16_s;
|
|
wire up_ch_ready_16_s;
|
|
wire [15:0] up_ch_rdata_17_s;
|
|
wire up_ch_ready_17_s;
|
|
wire [15:0] up_ch_rdata_18_s;
|
|
wire up_ch_ready_18_s;
|
|
wire [15:0] up_ch_rdata_19_s;
|
|
wire up_ch_ready_19_s;
|
|
wire [15:0] up_ch_rdata_20_s;
|
|
wire up_ch_ready_20_s;
|
|
wire [15:0] up_ch_rdata_21_s;
|
|
wire up_ch_ready_21_s;
|
|
wire [15:0] up_ch_rdata_22_s;
|
|
wire up_ch_ready_22_s;
|
|
wire [15:0] up_ch_rdata_23_s;
|
|
wire up_ch_ready_23_s;
|
|
wire [15:0] up_ch_rdata_24_s;
|
|
wire up_ch_ready_24_s;
|
|
wire [15:0] up_ch_rdata_25_s;
|
|
wire up_ch_ready_25_s;
|
|
wire [15:0] up_ch_rdata_26_s;
|
|
wire up_ch_ready_26_s;
|
|
wire [15:0] up_ch_rdata_27_s;
|
|
wire up_ch_ready_27_s;
|
|
wire [15:0] up_ch_rdata_28_s;
|
|
wire up_ch_ready_28_s;
|
|
wire [15:0] up_ch_rdata_29_s;
|
|
wire up_ch_ready_29_s;
|
|
wire [15:0] up_ch_rdata_30_s;
|
|
wire up_ch_ready_30_s;
|
|
wire [15:0] up_ch_rdata_31_s;
|
|
wire up_ch_ready_31_s;
|
|
wire up_es_req;
|
|
wire up_es_ack;
|
|
wire [ 4:0] up_es_pscale;
|
|
wire [ 1:0] up_es_vrange;
|
|
wire [ 7:0] up_es_vstep;
|
|
wire [ 7:0] up_es_vmax;
|
|
wire [ 7:0] up_es_vmin;
|
|
wire [11:0] up_es_hmax;
|
|
wire [11:0] up_es_hmin;
|
|
wire [11:0] up_es_hstep;
|
|
wire [31:0] up_es_saddr;
|
|
wire up_es_status;
|
|
wire up_rstn;
|
|
wire up_clk;
|
|
wire up_wreq;
|
|
wire [ 9:0] up_waddr;
|
|
wire [31:0] up_wdata;
|
|
wire up_wack;
|
|
wire up_rreq;
|
|
wire [ 9:0] up_raddr;
|
|
wire [31:0] up_rdata;
|
|
wire up_rack;
|
|
wire [15:0] up_es_reset;
|
|
|
|
assign up_es_reset_0 = up_es_reset[0];
|
|
assign up_es_reset_1 = up_es_reset[1];
|
|
assign up_es_reset_2 = up_es_reset[2];
|
|
assign up_es_reset_3 = up_es_reset[3];
|
|
assign up_es_reset_4 = up_es_reset[4];
|
|
assign up_es_reset_5 = up_es_reset[5];
|
|
assign up_es_reset_6 = up_es_reset[6];
|
|
assign up_es_reset_7 = up_es_reset[7];
|
|
assign up_es_reset_8 = up_es_reset[8];
|
|
assign up_es_reset_9 = up_es_reset[9];
|
|
assign up_es_reset_10 = up_es_reset[10];
|
|
assign up_es_reset_11 = up_es_reset[11];
|
|
assign up_es_reset_12 = up_es_reset[12];
|
|
assign up_es_reset_13 = up_es_reset[13];
|
|
assign up_es_reset_14 = up_es_reset[14];
|
|
assign up_es_reset_15 = up_es_reset[15];
|
|
|
|
// channel broadcast
|
|
|
|
assign up_rstn = s_axi_aresetn;
|
|
assign up_clk = s_axi_aclk;
|
|
|
|
assign up_cm_addr_0 = up_cm_addr;
|
|
assign up_cm_wr_0 = up_cm_wr;
|
|
assign up_cm_wdata_0 = up_cm_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (0),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_cm_0 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_cm_sel),
|
|
.up_enb (up_cm_enb),
|
|
.up_enb_out (up_cm_enb_0),
|
|
.up_rdata_in (16'd0),
|
|
.up_ready_in (1'd0),
|
|
.up_rdata (up_cm_rdata_0),
|
|
.up_ready (up_cm_ready_0),
|
|
.up_rdata_out (up_cm_rdata_0_s),
|
|
.up_ready_out (up_cm_ready_0_s));
|
|
|
|
assign up_es_addr_0 = up_es_addr;
|
|
assign up_es_wr_0 = up_es_wr;
|
|
assign up_es_wdata_0 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (0),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_0 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_0),
|
|
.up_rdata_in (16'd0),
|
|
.up_ready_in (1'd0),
|
|
.up_rdata (up_es_rdata_0),
|
|
.up_ready (up_es_ready_0),
|
|
.up_rdata_out (up_es_rdata_0_s),
|
|
.up_ready_out (up_es_ready_0_s));
|
|
|
|
assign up_ch_rst_0 = up_ch_rst;
|
|
assign up_ch_user_ready_0 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_0 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_0 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_0 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_0 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_0 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_0 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_0 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_0 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_0 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_0 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_0 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (0),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_0 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (1'd1),
|
|
.up_rst_done_in (1'd1),
|
|
.up_prbserr_in (1'd0),
|
|
.up_prbslocked_in (1'd1),
|
|
.up_bufstatus_in (2'd00),
|
|
.up_pll_locked (up_ch_pll_locked_0),
|
|
.up_rst_done (up_ch_rst_done_0),
|
|
.up_prbserr (up_ch_prbserr_0),
|
|
.up_prbslocked (up_ch_prbslocked_0),
|
|
.up_bufstatus (up_ch_bufstatus_0),
|
|
.up_pll_locked_out (up_ch_pll_locked_0_s),
|
|
.up_rst_done_out (up_ch_rst_done_0_s),
|
|
.up_prbserr_out (up_ch_prbserr_0_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_0_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_0_s));
|
|
|
|
assign up_ch_addr_0 = up_ch_addr;
|
|
assign up_ch_wr_0 = up_ch_wr;
|
|
assign up_ch_wdata_0 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (0),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_0 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_0),
|
|
.up_rdata_in (16'd0),
|
|
.up_ready_in (1'd0),
|
|
.up_rdata (up_ch_rdata_0),
|
|
.up_ready (up_ch_ready_0),
|
|
.up_rdata_out (up_ch_rdata_0_s),
|
|
.up_ready_out (up_ch_ready_0_s));
|
|
|
|
assign up_es_addr_1 = up_es_addr;
|
|
assign up_es_wr_1 = up_es_wr;
|
|
assign up_es_wdata_1 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (1),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_1 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_1),
|
|
.up_rdata_in (up_es_rdata_0_s),
|
|
.up_ready_in (up_es_ready_0_s),
|
|
.up_rdata (up_es_rdata_1),
|
|
.up_ready (up_es_ready_1),
|
|
.up_rdata_out (up_es_rdata_1_s),
|
|
.up_ready_out (up_es_ready_1_s));
|
|
|
|
assign up_ch_rst_1 = up_ch_rst;
|
|
assign up_ch_user_ready_1 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_1 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_1 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_1 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_1 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_1 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_1 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_1 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_1 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_1 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_1 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_1 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (1),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_1 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_0_s),
|
|
.up_rst_done_in (up_ch_rst_done_0_s),
|
|
.up_prbserr_in (up_ch_prbserr_0_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_0_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_0_s),
|
|
.up_pll_locked (up_ch_pll_locked_1),
|
|
.up_rst_done (up_ch_rst_done_1),
|
|
.up_prbserr (up_ch_prbserr_1),
|
|
.up_prbslocked (up_ch_prbslocked_1),
|
|
.up_bufstatus (up_ch_bufstatus_1),
|
|
.up_pll_locked_out (up_ch_pll_locked_1_s),
|
|
.up_rst_done_out (up_ch_rst_done_1_s),
|
|
.up_prbserr_out (up_ch_prbserr_1_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_1_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_1_s));
|
|
|
|
assign up_ch_addr_1 = up_ch_addr;
|
|
assign up_ch_wr_1 = up_ch_wr;
|
|
assign up_ch_wdata_1 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (1),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_1 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_1),
|
|
.up_rdata_in (up_ch_rdata_0_s),
|
|
.up_ready_in (up_ch_ready_0_s),
|
|
.up_rdata (up_ch_rdata_1),
|
|
.up_ready (up_ch_ready_1),
|
|
.up_rdata_out (up_ch_rdata_1_s),
|
|
.up_ready_out (up_ch_ready_1_s));
|
|
|
|
assign up_es_addr_2 = up_es_addr;
|
|
assign up_es_wr_2 = up_es_wr;
|
|
assign up_es_wdata_2 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (2),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_2 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_2),
|
|
.up_rdata_in (up_es_rdata_1_s),
|
|
.up_ready_in (up_es_ready_1_s),
|
|
.up_rdata (up_es_rdata_2),
|
|
.up_ready (up_es_ready_2),
|
|
.up_rdata_out (up_es_rdata_2_s),
|
|
.up_ready_out (up_es_ready_2_s));
|
|
|
|
assign up_ch_rst_2 = up_ch_rst;
|
|
assign up_ch_user_ready_2 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_2 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_2 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_2 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_2 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_2 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_2 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_2 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_2 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_2 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_2 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_2 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (2),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_2 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_1_s),
|
|
.up_rst_done_in (up_ch_rst_done_1_s),
|
|
.up_prbserr_in (up_ch_prbserr_1_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_1_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_1_s),
|
|
.up_pll_locked (up_ch_pll_locked_2),
|
|
.up_rst_done (up_ch_rst_done_2),
|
|
.up_prbserr (up_ch_prbserr_2),
|
|
.up_prbslocked (up_ch_prbslocked_2),
|
|
.up_bufstatus (up_ch_bufstatus_2),
|
|
.up_pll_locked_out (up_ch_pll_locked_2_s),
|
|
.up_rst_done_out (up_ch_rst_done_2_s),
|
|
.up_prbserr_out (up_ch_prbserr_2_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_2_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_2_s));
|
|
|
|
assign up_ch_addr_2 = up_ch_addr;
|
|
assign up_ch_wr_2 = up_ch_wr;
|
|
assign up_ch_wdata_2 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (2),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_2 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_2),
|
|
.up_rdata_in (up_ch_rdata_1_s),
|
|
.up_ready_in (up_ch_ready_1_s),
|
|
.up_rdata (up_ch_rdata_2),
|
|
.up_ready (up_ch_ready_2),
|
|
.up_rdata_out (up_ch_rdata_2_s),
|
|
.up_ready_out (up_ch_ready_2_s));
|
|
|
|
assign up_es_addr_3 = up_es_addr;
|
|
assign up_es_wr_3 = up_es_wr;
|
|
assign up_es_wdata_3 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (3),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_3 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_3),
|
|
.up_rdata_in (up_es_rdata_2_s),
|
|
.up_ready_in (up_es_ready_2_s),
|
|
.up_rdata (up_es_rdata_3),
|
|
.up_ready (up_es_ready_3),
|
|
.up_rdata_out (up_es_rdata_3_s),
|
|
.up_ready_out (up_es_ready_3_s));
|
|
|
|
assign up_ch_rst_3 = up_ch_rst;
|
|
assign up_ch_user_ready_3 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_3 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_3 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_3 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_3 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_3 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_3 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_3 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_3 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_3 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_3 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_3 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (3),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_3 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_2_s),
|
|
.up_rst_done_in (up_ch_rst_done_2_s),
|
|
.up_prbserr_in (up_ch_prbserr_2_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_2_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_2_s),
|
|
.up_pll_locked (up_ch_pll_locked_3),
|
|
.up_rst_done (up_ch_rst_done_3),
|
|
.up_prbserr (up_ch_prbserr_3),
|
|
.up_prbslocked (up_ch_prbslocked_3),
|
|
.up_bufstatus (up_ch_bufstatus_3),
|
|
.up_pll_locked_out (up_ch_pll_locked_3_s),
|
|
.up_rst_done_out (up_ch_rst_done_3_s),
|
|
.up_prbserr_out (up_ch_prbserr_3_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_3_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_3_s));
|
|
|
|
assign up_ch_addr_3 = up_ch_addr;
|
|
assign up_ch_wr_3 = up_ch_wr;
|
|
assign up_ch_wdata_3 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (3),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_3 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_3),
|
|
.up_rdata_in (up_ch_rdata_2_s),
|
|
.up_ready_in (up_ch_ready_2_s),
|
|
.up_rdata (up_ch_rdata_3),
|
|
.up_ready (up_ch_ready_3),
|
|
.up_rdata_out (up_ch_rdata_3_s),
|
|
.up_ready_out (up_ch_ready_3_s));
|
|
|
|
assign up_cm_addr_4 = up_cm_addr;
|
|
assign up_cm_wr_4 = up_cm_wr;
|
|
assign up_cm_wdata_4 = up_cm_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (4),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_cm_4 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_cm_sel),
|
|
.up_enb (up_cm_enb),
|
|
.up_enb_out (up_cm_enb_4),
|
|
.up_rdata_in (up_cm_rdata_0_s),
|
|
.up_ready_in (up_cm_ready_0_s),
|
|
.up_rdata (up_cm_rdata_4),
|
|
.up_ready (up_cm_ready_4),
|
|
.up_rdata_out (up_cm_rdata_4_s),
|
|
.up_ready_out (up_cm_ready_4_s));
|
|
|
|
assign up_es_addr_4 = up_es_addr;
|
|
assign up_es_wr_4 = up_es_wr;
|
|
assign up_es_wdata_4 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (4),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_4 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_4),
|
|
.up_rdata_in (up_es_rdata_3_s),
|
|
.up_ready_in (up_es_ready_3_s),
|
|
.up_rdata (up_es_rdata_4),
|
|
.up_ready (up_es_ready_4),
|
|
.up_rdata_out (up_es_rdata_4_s),
|
|
.up_ready_out (up_es_ready_4_s));
|
|
|
|
assign up_ch_rst_4 = up_ch_rst;
|
|
assign up_ch_user_ready_4 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_4 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_4 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_4 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_4 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_4 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_4 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_4 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_4 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_4 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_4 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_4 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (4),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_4 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_3_s),
|
|
.up_rst_done_in (up_ch_rst_done_3_s),
|
|
.up_prbserr_in (up_ch_prbserr_3_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_3_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_3_s),
|
|
.up_pll_locked (up_ch_pll_locked_4),
|
|
.up_rst_done (up_ch_rst_done_4),
|
|
.up_prbserr (up_ch_prbserr_4),
|
|
.up_prbslocked (up_ch_prbslocked_4),
|
|
.up_bufstatus (up_ch_bufstatus_4),
|
|
.up_pll_locked_out (up_ch_pll_locked_4_s),
|
|
.up_rst_done_out (up_ch_rst_done_4_s),
|
|
.up_prbserr_out (up_ch_prbserr_4_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_4_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_4_s));
|
|
|
|
assign up_ch_addr_4 = up_ch_addr;
|
|
assign up_ch_wr_4 = up_ch_wr;
|
|
assign up_ch_wdata_4 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (4),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_4 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_4),
|
|
.up_rdata_in (up_ch_rdata_3_s),
|
|
.up_ready_in (up_ch_ready_3_s),
|
|
.up_rdata (up_ch_rdata_4),
|
|
.up_ready (up_ch_ready_4),
|
|
.up_rdata_out (up_ch_rdata_4_s),
|
|
.up_ready_out (up_ch_ready_4_s));
|
|
|
|
assign up_es_addr_5 = up_es_addr;
|
|
assign up_es_wr_5 = up_es_wr;
|
|
assign up_es_wdata_5 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (5),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_5 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_5),
|
|
.up_rdata_in (up_es_rdata_4_s),
|
|
.up_ready_in (up_es_ready_4_s),
|
|
.up_rdata (up_es_rdata_5),
|
|
.up_ready (up_es_ready_5),
|
|
.up_rdata_out (up_es_rdata_5_s),
|
|
.up_ready_out (up_es_ready_5_s));
|
|
|
|
assign up_ch_rst_5 = up_ch_rst;
|
|
assign up_ch_user_ready_5 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_5 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_5 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_5 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_5 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_5 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_5 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_5 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_5 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_5 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_5 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_5 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (5),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_5 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_4_s),
|
|
.up_rst_done_in (up_ch_rst_done_4_s),
|
|
.up_prbserr_in (up_ch_prbserr_4_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_4_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_4_s),
|
|
.up_pll_locked (up_ch_pll_locked_5),
|
|
.up_rst_done (up_ch_rst_done_5),
|
|
.up_prbserr (up_ch_prbserr_5),
|
|
.up_prbslocked (up_ch_prbslocked_5),
|
|
.up_bufstatus (up_ch_bufstatus_5),
|
|
.up_pll_locked_out (up_ch_pll_locked_5_s),
|
|
.up_rst_done_out (up_ch_rst_done_5_s),
|
|
.up_prbserr_out (up_ch_prbserr_5_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_5_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_5_s));
|
|
|
|
assign up_ch_addr_5 = up_ch_addr;
|
|
assign up_ch_wr_5 = up_ch_wr;
|
|
assign up_ch_wdata_5 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (5),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_5 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_5),
|
|
.up_rdata_in (up_ch_rdata_4_s),
|
|
.up_ready_in (up_ch_ready_4_s),
|
|
.up_rdata (up_ch_rdata_5),
|
|
.up_ready (up_ch_ready_5),
|
|
.up_rdata_out (up_ch_rdata_5_s),
|
|
.up_ready_out (up_ch_ready_5_s));
|
|
|
|
assign up_es_addr_6 = up_es_addr;
|
|
assign up_es_wr_6 = up_es_wr;
|
|
assign up_es_wdata_6 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (6),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_6 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_6),
|
|
.up_rdata_in (up_es_rdata_5_s),
|
|
.up_ready_in (up_es_ready_5_s),
|
|
.up_rdata (up_es_rdata_6),
|
|
.up_ready (up_es_ready_6),
|
|
.up_rdata_out (up_es_rdata_6_s),
|
|
.up_ready_out (up_es_ready_6_s));
|
|
|
|
assign up_ch_rst_6 = up_ch_rst;
|
|
assign up_ch_user_ready_6 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_6 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_6 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_6 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_6 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_6 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_6 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_6 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_6 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_6 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_6 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_6 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (6),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_6 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_5_s),
|
|
.up_rst_done_in (up_ch_rst_done_5_s),
|
|
.up_prbserr_in (up_ch_prbserr_5_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_5_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_5_s),
|
|
.up_pll_locked (up_ch_pll_locked_6),
|
|
.up_rst_done (up_ch_rst_done_6),
|
|
.up_prbserr (up_ch_prbserr_6),
|
|
.up_prbslocked (up_ch_prbslocked_6),
|
|
.up_bufstatus (up_ch_bufstatus_6),
|
|
.up_pll_locked_out (up_ch_pll_locked_6_s),
|
|
.up_rst_done_out (up_ch_rst_done_6_s),
|
|
.up_prbserr_out (up_ch_prbserr_6_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_6_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_6_s));
|
|
|
|
assign up_ch_addr_6 = up_ch_addr;
|
|
assign up_ch_wr_6 = up_ch_wr;
|
|
assign up_ch_wdata_6 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (6),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_6 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_6),
|
|
.up_rdata_in (up_ch_rdata_5_s),
|
|
.up_ready_in (up_ch_ready_5_s),
|
|
.up_rdata (up_ch_rdata_6),
|
|
.up_ready (up_ch_ready_6),
|
|
.up_rdata_out (up_ch_rdata_6_s),
|
|
.up_ready_out (up_ch_ready_6_s));
|
|
|
|
assign up_es_addr_7 = up_es_addr;
|
|
assign up_es_wr_7 = up_es_wr;
|
|
assign up_es_wdata_7 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (7),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_7 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_7),
|
|
.up_rdata_in (up_es_rdata_6_s),
|
|
.up_ready_in (up_es_ready_6_s),
|
|
.up_rdata (up_es_rdata_7),
|
|
.up_ready (up_es_ready_7),
|
|
.up_rdata_out (up_es_rdata_7_s),
|
|
.up_ready_out (up_es_ready_7_s));
|
|
|
|
assign up_ch_rst_7 = up_ch_rst;
|
|
assign up_ch_user_ready_7 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_7 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_7 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_7 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_7 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_7 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_7 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_7 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_7 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_7 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_7 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_7 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (7),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_7 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_6_s),
|
|
.up_rst_done_in (up_ch_rst_done_6_s),
|
|
.up_prbserr_in (up_ch_prbserr_6_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_6_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_6_s),
|
|
.up_pll_locked (up_ch_pll_locked_7),
|
|
.up_rst_done (up_ch_rst_done_7),
|
|
.up_prbserr (up_ch_prbserr_7),
|
|
.up_prbslocked (up_ch_prbslocked_7),
|
|
.up_bufstatus (up_ch_bufstatus_7),
|
|
.up_pll_locked_out (up_ch_pll_locked_7_s),
|
|
.up_rst_done_out (up_ch_rst_done_7_s),
|
|
.up_prbserr_out (up_ch_prbserr_7_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_7_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_7_s));
|
|
|
|
assign up_ch_addr_7 = up_ch_addr;
|
|
assign up_ch_wr_7 = up_ch_wr;
|
|
assign up_ch_wdata_7 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (7),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_7 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_7),
|
|
.up_rdata_in (up_ch_rdata_6_s),
|
|
.up_ready_in (up_ch_ready_6_s),
|
|
.up_rdata (up_ch_rdata_7),
|
|
.up_ready (up_ch_ready_7),
|
|
.up_rdata_out (up_ch_rdata_7_s),
|
|
.up_ready_out (up_ch_ready_7_s));
|
|
|
|
assign up_cm_addr_8 = up_cm_addr;
|
|
assign up_cm_wr_8 = up_cm_wr;
|
|
assign up_cm_wdata_8 = up_cm_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (8),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_cm_8 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_cm_sel),
|
|
.up_enb (up_cm_enb),
|
|
.up_enb_out (up_cm_enb_8),
|
|
.up_rdata_in (up_cm_rdata_4_s),
|
|
.up_ready_in (up_cm_ready_4_s),
|
|
.up_rdata (up_cm_rdata_8),
|
|
.up_ready (up_cm_ready_8),
|
|
.up_rdata_out (up_cm_rdata_8_s),
|
|
.up_ready_out (up_cm_ready_8_s));
|
|
|
|
assign up_es_addr_8 = up_es_addr;
|
|
assign up_es_wr_8 = up_es_wr;
|
|
assign up_es_wdata_8 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (8),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_8 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_8),
|
|
.up_rdata_in (up_es_rdata_7_s),
|
|
.up_ready_in (up_es_ready_7_s),
|
|
.up_rdata (up_es_rdata_8),
|
|
.up_ready (up_es_ready_8),
|
|
.up_rdata_out (up_es_rdata_8_s),
|
|
.up_ready_out (up_es_ready_8_s));
|
|
|
|
assign up_ch_rst_8 = up_ch_rst;
|
|
assign up_ch_user_ready_8 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_8 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_8 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_8 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_8 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_8 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_8 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_8 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_8 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_8 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_8 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_8 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (8),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_8 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_7_s),
|
|
.up_rst_done_in (up_ch_rst_done_7_s),
|
|
.up_prbserr_in (up_ch_prbserr_7_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_7_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_7_s),
|
|
.up_pll_locked (up_ch_pll_locked_8),
|
|
.up_rst_done (up_ch_rst_done_8),
|
|
.up_prbserr (up_ch_prbserr_8),
|
|
.up_prbslocked (up_ch_prbslocked_8),
|
|
.up_bufstatus (up_ch_bufstatus_8),
|
|
.up_pll_locked_out (up_ch_pll_locked_8_s),
|
|
.up_rst_done_out (up_ch_rst_done_8_s),
|
|
.up_prbserr_out (up_ch_prbserr_8_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_8_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_8_s));
|
|
|
|
assign up_ch_addr_8 = up_ch_addr;
|
|
assign up_ch_wr_8 = up_ch_wr;
|
|
assign up_ch_wdata_8 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (8),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_8 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_8),
|
|
.up_rdata_in (up_ch_rdata_7_s),
|
|
.up_ready_in (up_ch_ready_7_s),
|
|
.up_rdata (up_ch_rdata_8),
|
|
.up_ready (up_ch_ready_8),
|
|
.up_rdata_out (up_ch_rdata_8_s),
|
|
.up_ready_out (up_ch_ready_8_s));
|
|
|
|
assign up_es_addr_9 = up_es_addr;
|
|
assign up_es_wr_9 = up_es_wr;
|
|
assign up_es_wdata_9 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (9),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_9 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_9),
|
|
.up_rdata_in (up_es_rdata_8_s),
|
|
.up_ready_in (up_es_ready_8_s),
|
|
.up_rdata (up_es_rdata_9),
|
|
.up_ready (up_es_ready_9),
|
|
.up_rdata_out (up_es_rdata_9_s),
|
|
.up_ready_out (up_es_ready_9_s));
|
|
|
|
assign up_ch_rst_9 = up_ch_rst;
|
|
assign up_ch_user_ready_9 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_9 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_9 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_9 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_9 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_9 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_9 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_9 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_9 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_9 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_9 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_9 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (9),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_9 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_8_s),
|
|
.up_rst_done_in (up_ch_rst_done_8_s),
|
|
.up_prbserr_in (up_ch_prbserr_8_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_8_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_8_s),
|
|
.up_pll_locked (up_ch_pll_locked_9),
|
|
.up_rst_done (up_ch_rst_done_9),
|
|
.up_prbserr (up_ch_prbserr_9),
|
|
.up_prbslocked (up_ch_prbslocked_9),
|
|
.up_bufstatus (up_ch_bufstatus_9),
|
|
.up_pll_locked_out (up_ch_pll_locked_9_s),
|
|
.up_rst_done_out (up_ch_rst_done_9_s),
|
|
.up_prbserr_out (up_ch_prbserr_9_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_9_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_9_s));
|
|
|
|
assign up_ch_addr_9 = up_ch_addr;
|
|
assign up_ch_wr_9 = up_ch_wr;
|
|
assign up_ch_wdata_9 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (9),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_9 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_9),
|
|
.up_rdata_in (up_ch_rdata_8_s),
|
|
.up_ready_in (up_ch_ready_8_s),
|
|
.up_rdata (up_ch_rdata_9),
|
|
.up_ready (up_ch_ready_9),
|
|
.up_rdata_out (up_ch_rdata_9_s),
|
|
.up_ready_out (up_ch_ready_9_s));
|
|
|
|
assign up_es_addr_10 = up_es_addr;
|
|
assign up_es_wr_10 = up_es_wr;
|
|
assign up_es_wdata_10 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (10),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_10 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_10),
|
|
.up_rdata_in (up_es_rdata_9_s),
|
|
.up_ready_in (up_es_ready_9_s),
|
|
.up_rdata (up_es_rdata_10),
|
|
.up_ready (up_es_ready_10),
|
|
.up_rdata_out (up_es_rdata_10_s),
|
|
.up_ready_out (up_es_ready_10_s));
|
|
|
|
assign up_ch_rst_10 = up_ch_rst;
|
|
assign up_ch_user_ready_10 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_10 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_10 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_10 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_10 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_10 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_10 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_10 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_10 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_10 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_10 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_10 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (10),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_10 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_9_s),
|
|
.up_rst_done_in (up_ch_rst_done_9_s),
|
|
.up_prbserr_in (up_ch_prbserr_9_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_9_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_9_s),
|
|
.up_pll_locked (up_ch_pll_locked_10),
|
|
.up_rst_done (up_ch_rst_done_10),
|
|
.up_prbserr (up_ch_prbserr_10),
|
|
.up_prbslocked (up_ch_prbslocked_10),
|
|
.up_bufstatus (up_ch_bufstatus_10),
|
|
.up_pll_locked_out (up_ch_pll_locked_10_s),
|
|
.up_rst_done_out (up_ch_rst_done_10_s),
|
|
.up_prbserr_out (up_ch_prbserr_10_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_10_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_10_s));
|
|
|
|
assign up_ch_addr_10 = up_ch_addr;
|
|
assign up_ch_wr_10 = up_ch_wr;
|
|
assign up_ch_wdata_10 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (10),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_10 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_10),
|
|
.up_rdata_in (up_ch_rdata_9_s),
|
|
.up_ready_in (up_ch_ready_9_s),
|
|
.up_rdata (up_ch_rdata_10),
|
|
.up_ready (up_ch_ready_10),
|
|
.up_rdata_out (up_ch_rdata_10_s),
|
|
.up_ready_out (up_ch_ready_10_s));
|
|
|
|
assign up_es_addr_11 = up_es_addr;
|
|
assign up_es_wr_11 = up_es_wr;
|
|
assign up_es_wdata_11 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (11),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_11 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_11),
|
|
.up_rdata_in (up_es_rdata_10_s),
|
|
.up_ready_in (up_es_ready_10_s),
|
|
.up_rdata (up_es_rdata_11),
|
|
.up_ready (up_es_ready_11),
|
|
.up_rdata_out (up_es_rdata_11_s),
|
|
.up_ready_out (up_es_ready_11_s));
|
|
|
|
assign up_ch_rst_11 = up_ch_rst;
|
|
assign up_ch_user_ready_11 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_11 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_11 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_11 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_11 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_11 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_11 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_11 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_11 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_11 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_11 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_11 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (11),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_11 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_10_s),
|
|
.up_rst_done_in (up_ch_rst_done_10_s),
|
|
.up_prbserr_in (up_ch_prbserr_10_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_10_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_10_s),
|
|
.up_pll_locked (up_ch_pll_locked_11),
|
|
.up_rst_done (up_ch_rst_done_11),
|
|
.up_prbserr (up_ch_prbserr_11),
|
|
.up_prbslocked (up_ch_prbslocked_11),
|
|
.up_bufstatus (up_ch_bufstatus_11),
|
|
.up_pll_locked_out (up_ch_pll_locked_11_s),
|
|
.up_rst_done_out (up_ch_rst_done_11_s),
|
|
.up_prbserr_out (up_ch_prbserr_11_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_11_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_11_s));
|
|
|
|
assign up_ch_addr_11 = up_ch_addr;
|
|
assign up_ch_wr_11 = up_ch_wr;
|
|
assign up_ch_wdata_11 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (11),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_11 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_11),
|
|
.up_rdata_in (up_ch_rdata_10_s),
|
|
.up_ready_in (up_ch_ready_10_s),
|
|
.up_rdata (up_ch_rdata_11),
|
|
.up_ready (up_ch_ready_11),
|
|
.up_rdata_out (up_ch_rdata_11_s),
|
|
.up_ready_out (up_ch_ready_11_s));
|
|
|
|
assign up_cm_addr_12 = up_cm_addr;
|
|
assign up_cm_wr_12 = up_cm_wr;
|
|
assign up_cm_wdata_12 = up_cm_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (12),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_cm_12 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_cm_sel),
|
|
.up_enb (up_cm_enb),
|
|
.up_enb_out (up_cm_enb_12),
|
|
.up_rdata_in (up_cm_rdata_8_s),
|
|
.up_ready_in (up_cm_ready_8_s),
|
|
.up_rdata (up_cm_rdata_12),
|
|
.up_ready (up_cm_ready_12),
|
|
.up_rdata_out (up_cm_rdata_12_s),
|
|
.up_ready_out (up_cm_ready_12_s));
|
|
|
|
assign up_es_addr_12 = up_es_addr;
|
|
assign up_es_wr_12 = up_es_wr;
|
|
assign up_es_wdata_12 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (12),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_12 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_12),
|
|
.up_rdata_in (up_es_rdata_11_s),
|
|
.up_ready_in (up_es_ready_11_s),
|
|
.up_rdata (up_es_rdata_12),
|
|
.up_ready (up_es_ready_12),
|
|
.up_rdata_out (up_es_rdata_12_s),
|
|
.up_ready_out (up_es_ready_12_s));
|
|
|
|
assign up_ch_rst_12 = up_ch_rst;
|
|
assign up_ch_user_ready_12 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_12 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_12 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_12 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_12 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_12 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_12 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_12 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_12 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_12 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_12 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_12 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (12),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_12 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_11_s),
|
|
.up_rst_done_in (up_ch_rst_done_11_s),
|
|
.up_prbserr_in (up_ch_prbserr_11_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_11_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_11_s),
|
|
.up_pll_locked (up_ch_pll_locked_12),
|
|
.up_rst_done (up_ch_rst_done_12),
|
|
.up_prbserr (up_ch_prbserr_12),
|
|
.up_prbslocked (up_ch_prbslocked_12),
|
|
.up_bufstatus (up_ch_bufstatus_12),
|
|
.up_pll_locked_out (up_ch_pll_locked_12_s),
|
|
.up_rst_done_out (up_ch_rst_done_12_s),
|
|
.up_prbserr_out (up_ch_prbserr_12_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_12_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_12_s));
|
|
|
|
assign up_ch_addr_12 = up_ch_addr;
|
|
assign up_ch_wr_12 = up_ch_wr;
|
|
assign up_ch_wdata_12 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (12),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_12 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_12),
|
|
.up_rdata_in (up_ch_rdata_11_s),
|
|
.up_ready_in (up_ch_ready_11_s),
|
|
.up_rdata (up_ch_rdata_12),
|
|
.up_ready (up_ch_ready_12),
|
|
.up_rdata_out (up_ch_rdata_12_s),
|
|
.up_ready_out (up_ch_ready_12_s));
|
|
|
|
assign up_es_addr_13 = up_es_addr;
|
|
assign up_es_wr_13 = up_es_wr;
|
|
assign up_es_wdata_13 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (13),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_13 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_13),
|
|
.up_rdata_in (up_es_rdata_12_s),
|
|
.up_ready_in (up_es_ready_12_s),
|
|
.up_rdata (up_es_rdata_13),
|
|
.up_ready (up_es_ready_13),
|
|
.up_rdata_out (up_es_rdata_13_s),
|
|
.up_ready_out (up_es_ready_13_s));
|
|
|
|
assign up_ch_rst_13 = up_ch_rst;
|
|
assign up_ch_user_ready_13 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_13 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_13 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_13 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_13 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_13 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_13 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_13 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_13 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_13 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_13 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_13 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (13),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_13 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_12_s),
|
|
.up_rst_done_in (up_ch_rst_done_12_s),
|
|
.up_prbserr_in (up_ch_prbserr_12_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_12_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_12_s),
|
|
.up_pll_locked (up_ch_pll_locked_13),
|
|
.up_rst_done (up_ch_rst_done_13),
|
|
.up_prbserr (up_ch_prbserr_13),
|
|
.up_prbslocked (up_ch_prbslocked_13),
|
|
.up_bufstatus (up_ch_bufstatus_13),
|
|
.up_pll_locked_out (up_ch_pll_locked_13_s),
|
|
.up_rst_done_out (up_ch_rst_done_13_s),
|
|
.up_prbserr_out (up_ch_prbserr_13_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_13_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_13_s));
|
|
|
|
assign up_ch_addr_13 = up_ch_addr;
|
|
assign up_ch_wr_13 = up_ch_wr;
|
|
assign up_ch_wdata_13 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (13),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_13 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_13),
|
|
.up_rdata_in (up_ch_rdata_12_s),
|
|
.up_ready_in (up_ch_ready_12_s),
|
|
.up_rdata (up_ch_rdata_13),
|
|
.up_ready (up_ch_ready_13),
|
|
.up_rdata_out (up_ch_rdata_13_s),
|
|
.up_ready_out (up_ch_ready_13_s));
|
|
|
|
assign up_es_addr_14 = up_es_addr;
|
|
assign up_es_wr_14 = up_es_wr;
|
|
assign up_es_wdata_14 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (14),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_14 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_14),
|
|
.up_rdata_in (up_es_rdata_13_s),
|
|
.up_ready_in (up_es_ready_13_s),
|
|
.up_rdata (up_es_rdata_14),
|
|
.up_ready (up_es_ready_14),
|
|
.up_rdata_out (up_es_rdata_14_s),
|
|
.up_ready_out (up_es_ready_14_s));
|
|
|
|
assign up_ch_rst_14 = up_ch_rst;
|
|
assign up_ch_user_ready_14 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_14 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_14 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_14 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_14 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_14 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_14 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_14 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_14 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_14 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_14 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_14 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (14),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_14 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_13_s),
|
|
.up_rst_done_in (up_ch_rst_done_13_s),
|
|
.up_prbserr_in (up_ch_prbserr_13_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_13_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_13_s),
|
|
.up_pll_locked (up_ch_pll_locked_14),
|
|
.up_rst_done (up_ch_rst_done_14),
|
|
.up_prbserr (up_ch_prbserr_14),
|
|
.up_prbslocked (up_ch_prbslocked_14),
|
|
.up_bufstatus (up_ch_bufstatus_14),
|
|
.up_pll_locked_out (up_ch_pll_locked_14_s),
|
|
.up_rst_done_out (up_ch_rst_done_14_s),
|
|
.up_prbserr_out (up_ch_prbserr_14_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_14_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_14_s));
|
|
|
|
assign up_ch_addr_14 = up_ch_addr;
|
|
assign up_ch_wr_14 = up_ch_wr;
|
|
assign up_ch_wdata_14 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (14),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_14 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_14),
|
|
.up_rdata_in (up_ch_rdata_13_s),
|
|
.up_ready_in (up_ch_ready_13_s),
|
|
.up_rdata (up_ch_rdata_14),
|
|
.up_ready (up_ch_ready_14),
|
|
.up_rdata_out (up_ch_rdata_14_s),
|
|
.up_ready_out (up_ch_ready_14_s));
|
|
|
|
assign up_es_addr_15 = up_es_addr;
|
|
assign up_es_wr_15 = up_es_wr;
|
|
assign up_es_wdata_15 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (15),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_15 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_15),
|
|
.up_rdata_in (up_es_rdata_14_s),
|
|
.up_ready_in (up_es_ready_14_s),
|
|
.up_rdata (up_es_rdata_15),
|
|
.up_ready (up_es_ready_15),
|
|
.up_rdata_out (up_es_rdata_15_s),
|
|
.up_ready_out (up_es_ready_15_s));
|
|
|
|
assign up_ch_rst_15 = up_ch_rst;
|
|
assign up_ch_user_ready_15 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_15 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_15 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_15 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_15 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_15 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_15 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_15 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_15 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_15 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_15 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_15 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (15),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_15 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_14_s),
|
|
.up_rst_done_in (up_ch_rst_done_14_s),
|
|
.up_prbserr_in (up_ch_prbserr_14_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_14_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_14_s),
|
|
.up_pll_locked (up_ch_pll_locked_15),
|
|
.up_rst_done (up_ch_rst_done_15),
|
|
.up_prbserr (up_ch_prbserr_15),
|
|
.up_prbslocked (up_ch_prbslocked_15),
|
|
.up_bufstatus (up_ch_bufstatus_15),
|
|
.up_pll_locked_out (up_ch_pll_locked_15_s),
|
|
.up_rst_done_out (up_ch_rst_done_15_s),
|
|
.up_prbserr_out (up_ch_prbserr_15_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_15_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_15_s));
|
|
|
|
assign up_ch_addr_15 = up_ch_addr;
|
|
assign up_ch_wr_15 = up_ch_wr;
|
|
assign up_ch_wdata_15 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (15),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_15 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_15),
|
|
.up_rdata_in (up_ch_rdata_14_s),
|
|
.up_ready_in (up_ch_ready_14_s),
|
|
.up_rdata (up_ch_rdata_15),
|
|
.up_ready (up_ch_ready_15),
|
|
.up_rdata_out (up_ch_rdata_15_s),
|
|
.up_ready_out (up_ch_ready_15_s));
|
|
|
|
assign up_cm_addr_16 = up_cm_addr;
|
|
assign up_cm_wr_16 = up_cm_wr;
|
|
assign up_cm_wdata_16 = up_cm_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (16),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_cm_16 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_cm_sel),
|
|
.up_enb (up_cm_enb),
|
|
.up_enb_out (up_cm_enb_16),
|
|
.up_rdata_in (up_cm_rdata_12_s),
|
|
.up_ready_in (up_cm_ready_12_s),
|
|
.up_rdata (up_cm_rdata_16),
|
|
.up_ready (up_cm_ready_16),
|
|
.up_rdata_out (up_cm_rdata_16_s),
|
|
.up_ready_out (up_cm_ready_16_s));
|
|
|
|
assign up_es_addr_16 = up_es_addr;
|
|
assign up_es_wr_16 = up_es_wr;
|
|
assign up_es_wdata_16 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (16),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_16 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_16),
|
|
.up_rdata_in (up_es_rdata_15_s),
|
|
.up_ready_in (up_es_ready_15_s),
|
|
.up_rdata (up_es_rdata_16),
|
|
.up_ready (up_es_ready_16),
|
|
.up_rdata_out (up_es_rdata_16_s),
|
|
.up_ready_out (up_es_ready_16_s));
|
|
|
|
assign up_ch_rst_16 = up_ch_rst;
|
|
assign up_ch_user_ready_16 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_16 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_16 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_16 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_16 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_16 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_16 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_16 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_16 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_16 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_16 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_16 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (16),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_16 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_15_s),
|
|
.up_rst_done_in (up_ch_rst_done_15_s),
|
|
.up_prbserr_in (up_ch_prbserr_15_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_15_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_15_s),
|
|
.up_pll_locked (up_ch_pll_locked_16),
|
|
.up_rst_done (up_ch_rst_done_16),
|
|
.up_prbserr (up_ch_prbserr_16),
|
|
.up_prbslocked (up_ch_prbslocked_16),
|
|
.up_bufstatus (up_ch_bufstatus_16),
|
|
.up_pll_locked_out (up_ch_pll_locked_16_s),
|
|
.up_rst_done_out (up_ch_rst_done_16_s),
|
|
.up_prbserr_out (up_ch_prbserr_16_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_16_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_16_s));
|
|
|
|
assign up_ch_addr_16 = up_ch_addr;
|
|
assign up_ch_wr_16 = up_ch_wr;
|
|
assign up_ch_wdata_16 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (16),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_16 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_16),
|
|
.up_rdata_in (up_ch_rdata_15_s),
|
|
.up_ready_in (up_ch_ready_15_s),
|
|
.up_rdata (up_ch_rdata_16),
|
|
.up_ready (up_ch_ready_16),
|
|
.up_rdata_out (up_ch_rdata_16_s),
|
|
.up_ready_out (up_ch_ready_16_s));
|
|
|
|
assign up_es_addr_17 = up_es_addr;
|
|
assign up_es_wr_17 = up_es_wr;
|
|
assign up_es_wdata_17 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (17),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_17 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_17),
|
|
.up_rdata_in (up_es_rdata_16_s),
|
|
.up_ready_in (up_es_ready_16_s),
|
|
.up_rdata (up_es_rdata_17),
|
|
.up_ready (up_es_ready_17),
|
|
.up_rdata_out (up_es_rdata_17_s),
|
|
.up_ready_out (up_es_ready_17_s));
|
|
|
|
assign up_ch_rst_17 = up_ch_rst;
|
|
assign up_ch_user_ready_17 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_17 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_17 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_17 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_17 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_17 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_17 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_17 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_17 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_17 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_17 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_17 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (17),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_17 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_16_s),
|
|
.up_rst_done_in (up_ch_rst_done_16_s),
|
|
.up_prbserr_in (up_ch_prbserr_16_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_16_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_16_s),
|
|
.up_pll_locked (up_ch_pll_locked_17),
|
|
.up_rst_done (up_ch_rst_done_17),
|
|
.up_prbserr (up_ch_prbserr_17),
|
|
.up_prbslocked (up_ch_prbslocked_17),
|
|
.up_bufstatus (up_ch_bufstatus_17),
|
|
.up_pll_locked_out (up_ch_pll_locked_17_s),
|
|
.up_rst_done_out (up_ch_rst_done_17_s),
|
|
.up_prbserr_out (up_ch_prbserr_17_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_17_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_17_s));
|
|
|
|
assign up_ch_addr_17 = up_ch_addr;
|
|
assign up_ch_wr_17 = up_ch_wr;
|
|
assign up_ch_wdata_17 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (17),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_17 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_17),
|
|
.up_rdata_in (up_ch_rdata_16_s),
|
|
.up_ready_in (up_ch_ready_16_s),
|
|
.up_rdata (up_ch_rdata_17),
|
|
.up_ready (up_ch_ready_17),
|
|
.up_rdata_out (up_ch_rdata_17_s),
|
|
.up_ready_out (up_ch_ready_17_s));
|
|
|
|
assign up_es_addr_18 = up_es_addr;
|
|
assign up_es_wr_18 = up_es_wr;
|
|
assign up_es_wdata_18 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (18),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_18 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_18),
|
|
.up_rdata_in (up_es_rdata_17_s),
|
|
.up_ready_in (up_es_ready_17_s),
|
|
.up_rdata (up_es_rdata_18),
|
|
.up_ready (up_es_ready_18),
|
|
.up_rdata_out (up_es_rdata_18_s),
|
|
.up_ready_out (up_es_ready_18_s));
|
|
|
|
assign up_ch_rst_18 = up_ch_rst;
|
|
assign up_ch_user_ready_18 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_18 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_18 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_18 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_18 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_18 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_18 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_18 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_18 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_18 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_18 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_18 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (18),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_18 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_17_s),
|
|
.up_rst_done_in (up_ch_rst_done_17_s),
|
|
.up_prbserr_in (up_ch_prbserr_17_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_17_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_17_s),
|
|
.up_pll_locked (up_ch_pll_locked_18),
|
|
.up_rst_done (up_ch_rst_done_18),
|
|
.up_prbserr (up_ch_prbserr_18),
|
|
.up_prbslocked (up_ch_prbslocked_18),
|
|
.up_bufstatus (up_ch_bufstatus_18),
|
|
.up_pll_locked_out (up_ch_pll_locked_18_s),
|
|
.up_rst_done_out (up_ch_rst_done_18_s),
|
|
.up_prbserr_out (up_ch_prbserr_18_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_18_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_18_s));
|
|
|
|
assign up_ch_addr_18 = up_ch_addr;
|
|
assign up_ch_wr_18 = up_ch_wr;
|
|
assign up_ch_wdata_18 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (18),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_18 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_18),
|
|
.up_rdata_in (up_ch_rdata_17_s),
|
|
.up_ready_in (up_ch_ready_17_s),
|
|
.up_rdata (up_ch_rdata_18),
|
|
.up_ready (up_ch_ready_18),
|
|
.up_rdata_out (up_ch_rdata_18_s),
|
|
.up_ready_out (up_ch_ready_18_s));
|
|
|
|
assign up_es_addr_19 = up_es_addr;
|
|
assign up_es_wr_19 = up_es_wr;
|
|
assign up_es_wdata_19 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (19),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_19 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_19),
|
|
.up_rdata_in (up_es_rdata_18_s),
|
|
.up_ready_in (up_es_ready_18_s),
|
|
.up_rdata (up_es_rdata_19),
|
|
.up_ready (up_es_ready_19),
|
|
.up_rdata_out (up_es_rdata_19_s),
|
|
.up_ready_out (up_es_ready_19_s));
|
|
|
|
assign up_ch_rst_19 = up_ch_rst;
|
|
assign up_ch_user_ready_19 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_19 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_19 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_19 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_19 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_19 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_19 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_19 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_19 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_19 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_19 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_19 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (19),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_19 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_18_s),
|
|
.up_rst_done_in (up_ch_rst_done_18_s),
|
|
.up_prbserr_in (up_ch_prbserr_18_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_18_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_18_s),
|
|
.up_pll_locked (up_ch_pll_locked_19),
|
|
.up_rst_done (up_ch_rst_done_19),
|
|
.up_prbserr (up_ch_prbserr_19),
|
|
.up_prbslocked (up_ch_prbslocked_19),
|
|
.up_bufstatus (up_ch_bufstatus_19),
|
|
.up_pll_locked_out (up_ch_pll_locked_19_s),
|
|
.up_rst_done_out (up_ch_rst_done_19_s),
|
|
.up_prbserr_out (up_ch_prbserr_19_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_19_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_19_s));
|
|
|
|
assign up_ch_addr_19 = up_ch_addr;
|
|
assign up_ch_wr_19 = up_ch_wr;
|
|
assign up_ch_wdata_19 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (19),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_19 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_19),
|
|
.up_rdata_in (up_ch_rdata_18_s),
|
|
.up_ready_in (up_ch_ready_18_s),
|
|
.up_rdata (up_ch_rdata_19),
|
|
.up_ready (up_ch_ready_19),
|
|
.up_rdata_out (up_ch_rdata_19_s),
|
|
.up_ready_out (up_ch_ready_19_s));
|
|
|
|
assign up_cm_addr_20 = up_cm_addr;
|
|
assign up_cm_wr_20 = up_cm_wr;
|
|
assign up_cm_wdata_20 = up_cm_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (20),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_cm_20 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_cm_sel),
|
|
.up_enb (up_cm_enb),
|
|
.up_enb_out (up_cm_enb_20),
|
|
.up_rdata_in (up_cm_rdata_16_s),
|
|
.up_ready_in (up_cm_ready_16_s),
|
|
.up_rdata (up_cm_rdata_20),
|
|
.up_ready (up_cm_ready_20),
|
|
.up_rdata_out (up_cm_rdata_20_s),
|
|
.up_ready_out (up_cm_ready_20_s));
|
|
|
|
assign up_es_addr_20 = up_es_addr;
|
|
assign up_es_wr_20 = up_es_wr;
|
|
assign up_es_wdata_20 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (20),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_20 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_20),
|
|
.up_rdata_in (up_es_rdata_19_s),
|
|
.up_ready_in (up_es_ready_19_s),
|
|
.up_rdata (up_es_rdata_20),
|
|
.up_ready (up_es_ready_20),
|
|
.up_rdata_out (up_es_rdata_20_s),
|
|
.up_ready_out (up_es_ready_20_s));
|
|
|
|
assign up_ch_rst_20 = up_ch_rst;
|
|
assign up_ch_user_ready_20 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_20 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_20 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_20 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_20 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_20 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_20 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_20 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_20 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_20 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_20 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_20 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (20),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_20 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_19_s),
|
|
.up_rst_done_in (up_ch_rst_done_19_s),
|
|
.up_prbserr_in (up_ch_prbserr_19_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_19_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_19_s),
|
|
.up_pll_locked (up_ch_pll_locked_20),
|
|
.up_rst_done (up_ch_rst_done_20),
|
|
.up_prbserr (up_ch_prbserr_20),
|
|
.up_prbslocked (up_ch_prbslocked_20),
|
|
.up_bufstatus (up_ch_bufstatus_20),
|
|
.up_pll_locked_out (up_ch_pll_locked_20_s),
|
|
.up_rst_done_out (up_ch_rst_done_20_s),
|
|
.up_prbserr_out (up_ch_prbserr_20_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_20_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_20_s));
|
|
|
|
assign up_ch_addr_20 = up_ch_addr;
|
|
assign up_ch_wr_20 = up_ch_wr;
|
|
assign up_ch_wdata_20 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (20),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_20 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_20),
|
|
.up_rdata_in (up_ch_rdata_19_s),
|
|
.up_ready_in (up_ch_ready_19_s),
|
|
.up_rdata (up_ch_rdata_20),
|
|
.up_ready (up_ch_ready_20),
|
|
.up_rdata_out (up_ch_rdata_20_s),
|
|
.up_ready_out (up_ch_ready_20_s));
|
|
|
|
assign up_es_addr_21 = up_es_addr;
|
|
assign up_es_wr_21 = up_es_wr;
|
|
assign up_es_wdata_21 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (21),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_21 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_21),
|
|
.up_rdata_in (up_es_rdata_20_s),
|
|
.up_ready_in (up_es_ready_20_s),
|
|
.up_rdata (up_es_rdata_21),
|
|
.up_ready (up_es_ready_21),
|
|
.up_rdata_out (up_es_rdata_21_s),
|
|
.up_ready_out (up_es_ready_21_s));
|
|
|
|
assign up_ch_rst_21 = up_ch_rst;
|
|
assign up_ch_user_ready_21 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_21 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_21 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_21 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_21 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_21 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_21 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_21 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_21 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_21 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_21 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_21 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (21),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_21 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_20_s),
|
|
.up_rst_done_in (up_ch_rst_done_20_s),
|
|
.up_prbserr_in (up_ch_prbserr_20_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_20_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_20_s),
|
|
.up_pll_locked (up_ch_pll_locked_21),
|
|
.up_rst_done (up_ch_rst_done_21),
|
|
.up_prbserr (up_ch_prbserr_21),
|
|
.up_prbslocked (up_ch_prbslocked_21),
|
|
.up_bufstatus (up_ch_bufstatus_21),
|
|
.up_pll_locked_out (up_ch_pll_locked_21_s),
|
|
.up_rst_done_out (up_ch_rst_done_21_s),
|
|
.up_prbserr_out (up_ch_prbserr_21_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_21_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_21_s));
|
|
|
|
assign up_ch_addr_21 = up_ch_addr;
|
|
assign up_ch_wr_21 = up_ch_wr;
|
|
assign up_ch_wdata_21 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (21),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_21 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_21),
|
|
.up_rdata_in (up_ch_rdata_20_s),
|
|
.up_ready_in (up_ch_ready_20_s),
|
|
.up_rdata (up_ch_rdata_21),
|
|
.up_ready (up_ch_ready_21),
|
|
.up_rdata_out (up_ch_rdata_21_s),
|
|
.up_ready_out (up_ch_ready_21_s));
|
|
|
|
assign up_es_addr_22 = up_es_addr;
|
|
assign up_es_wr_22 = up_es_wr;
|
|
assign up_es_wdata_22 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (22),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_22 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_22),
|
|
.up_rdata_in (up_es_rdata_21_s),
|
|
.up_ready_in (up_es_ready_21_s),
|
|
.up_rdata (up_es_rdata_22),
|
|
.up_ready (up_es_ready_22),
|
|
.up_rdata_out (up_es_rdata_22_s),
|
|
.up_ready_out (up_es_ready_22_s));
|
|
|
|
assign up_ch_rst_22 = up_ch_rst;
|
|
assign up_ch_user_ready_22 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_22 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_22 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_22 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_22 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_22 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_22 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_22 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_22 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_22 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_22 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_22 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (22),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_22 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_21_s),
|
|
.up_rst_done_in (up_ch_rst_done_21_s),
|
|
.up_prbserr_in (up_ch_prbserr_21_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_21_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_21_s),
|
|
.up_pll_locked (up_ch_pll_locked_22),
|
|
.up_rst_done (up_ch_rst_done_22),
|
|
.up_prbserr (up_ch_prbserr_22),
|
|
.up_prbslocked (up_ch_prbslocked_22),
|
|
.up_bufstatus (up_ch_bufstatus_22),
|
|
.up_pll_locked_out (up_ch_pll_locked_22_s),
|
|
.up_rst_done_out (up_ch_rst_done_22_s),
|
|
.up_prbserr_out (up_ch_prbserr_22_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_22_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_22_s));
|
|
|
|
assign up_ch_addr_22 = up_ch_addr;
|
|
assign up_ch_wr_22 = up_ch_wr;
|
|
assign up_ch_wdata_22 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (22),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_22 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_22),
|
|
.up_rdata_in (up_ch_rdata_21_s),
|
|
.up_ready_in (up_ch_ready_21_s),
|
|
.up_rdata (up_ch_rdata_22),
|
|
.up_ready (up_ch_ready_22),
|
|
.up_rdata_out (up_ch_rdata_22_s),
|
|
.up_ready_out (up_ch_ready_22_s));
|
|
|
|
assign up_es_addr_23 = up_es_addr;
|
|
assign up_es_wr_23 = up_es_wr;
|
|
assign up_es_wdata_23 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (23),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_23 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_23),
|
|
.up_rdata_in (up_es_rdata_22_s),
|
|
.up_ready_in (up_es_ready_22_s),
|
|
.up_rdata (up_es_rdata_23),
|
|
.up_ready (up_es_ready_23),
|
|
.up_rdata_out (up_es_rdata_23_s),
|
|
.up_ready_out (up_es_ready_23_s));
|
|
|
|
assign up_ch_rst_23 = up_ch_rst;
|
|
assign up_ch_user_ready_23 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_23 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_23 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_23 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_23 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_23 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_23 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_23 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_23 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_23 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_23 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_23 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (23),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_23 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_22_s),
|
|
.up_rst_done_in (up_ch_rst_done_22_s),
|
|
.up_prbserr_in (up_ch_prbserr_22_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_22_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_22_s),
|
|
.up_pll_locked (up_ch_pll_locked_23),
|
|
.up_rst_done (up_ch_rst_done_23),
|
|
.up_prbserr (up_ch_prbserr_23),
|
|
.up_prbslocked (up_ch_prbslocked_23),
|
|
.up_bufstatus (up_ch_bufstatus_23),
|
|
.up_pll_locked_out (up_ch_pll_locked_23_s),
|
|
.up_rst_done_out (up_ch_rst_done_23_s),
|
|
.up_prbserr_out (up_ch_prbserr_23_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_23_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_23_s));
|
|
|
|
assign up_ch_addr_23 = up_ch_addr;
|
|
assign up_ch_wr_23 = up_ch_wr;
|
|
assign up_ch_wdata_23 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (23),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_23 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_23),
|
|
.up_rdata_in (up_ch_rdata_22_s),
|
|
.up_ready_in (up_ch_ready_22_s),
|
|
.up_rdata (up_ch_rdata_23),
|
|
.up_ready (up_ch_ready_23),
|
|
.up_rdata_out (up_ch_rdata_23_s),
|
|
.up_ready_out (up_ch_ready_23_s));
|
|
|
|
assign up_cm_addr_24 = up_cm_addr;
|
|
assign up_cm_wr_24 = up_cm_wr;
|
|
assign up_cm_wdata_24 = up_cm_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (24),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_cm_24 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_cm_sel),
|
|
.up_enb (up_cm_enb),
|
|
.up_enb_out (up_cm_enb_24),
|
|
.up_rdata_in (up_cm_rdata_20_s),
|
|
.up_ready_in (up_cm_ready_20_s),
|
|
.up_rdata (up_cm_rdata_24),
|
|
.up_ready (up_cm_ready_24),
|
|
.up_rdata_out (up_cm_rdata_24_s),
|
|
.up_ready_out (up_cm_ready_24_s));
|
|
|
|
assign up_es_addr_24 = up_es_addr;
|
|
assign up_es_wr_24 = up_es_wr;
|
|
assign up_es_wdata_24 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (24),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_24 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_24),
|
|
.up_rdata_in (up_es_rdata_23_s),
|
|
.up_ready_in (up_es_ready_23_s),
|
|
.up_rdata (up_es_rdata_24),
|
|
.up_ready (up_es_ready_24),
|
|
.up_rdata_out (up_es_rdata_24_s),
|
|
.up_ready_out (up_es_ready_24_s));
|
|
|
|
assign up_ch_rst_24 = up_ch_rst;
|
|
assign up_ch_user_ready_24 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_24 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_24 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_24 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_24 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_24 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_24 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_24 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_24 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_24 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_24 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_24 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (24),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_24 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_23_s),
|
|
.up_rst_done_in (up_ch_rst_done_23_s),
|
|
.up_prbserr_in (up_ch_prbserr_23_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_23_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_23_s),
|
|
.up_pll_locked (up_ch_pll_locked_24),
|
|
.up_rst_done (up_ch_rst_done_24),
|
|
.up_prbserr (up_ch_prbserr_24),
|
|
.up_prbslocked (up_ch_prbslocked_24),
|
|
.up_bufstatus (up_ch_bufstatus_24),
|
|
.up_pll_locked_out (up_ch_pll_locked_24_s),
|
|
.up_rst_done_out (up_ch_rst_done_24_s),
|
|
.up_prbserr_out (up_ch_prbserr_24_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_24_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_24_s));
|
|
|
|
assign up_ch_addr_24 = up_ch_addr;
|
|
assign up_ch_wr_24 = up_ch_wr;
|
|
assign up_ch_wdata_24 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (24),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_24 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_24),
|
|
.up_rdata_in (up_ch_rdata_23_s),
|
|
.up_ready_in (up_ch_ready_23_s),
|
|
.up_rdata (up_ch_rdata_24),
|
|
.up_ready (up_ch_ready_24),
|
|
.up_rdata_out (up_ch_rdata_24_s),
|
|
.up_ready_out (up_ch_ready_24_s));
|
|
|
|
assign up_es_addr_25 = up_es_addr;
|
|
assign up_es_wr_25 = up_es_wr;
|
|
assign up_es_wdata_25 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (25),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_25 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_25),
|
|
.up_rdata_in (up_es_rdata_24_s),
|
|
.up_ready_in (up_es_ready_24_s),
|
|
.up_rdata (up_es_rdata_25),
|
|
.up_ready (up_es_ready_25),
|
|
.up_rdata_out (up_es_rdata_25_s),
|
|
.up_ready_out (up_es_ready_25_s));
|
|
|
|
assign up_ch_rst_25 = up_ch_rst;
|
|
assign up_ch_user_ready_25 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_25 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_25 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_25 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_25 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_25 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_25 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_25 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_25 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_25 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_25 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_25 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (25),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_25 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_24_s),
|
|
.up_rst_done_in (up_ch_rst_done_24_s),
|
|
.up_prbserr_in (up_ch_prbserr_24_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_24_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_24_s),
|
|
.up_pll_locked (up_ch_pll_locked_25),
|
|
.up_rst_done (up_ch_rst_done_25),
|
|
.up_prbserr (up_ch_prbserr_25),
|
|
.up_prbslocked (up_ch_prbslocked_25),
|
|
.up_bufstatus (up_ch_bufstatus_25),
|
|
.up_pll_locked_out (up_ch_pll_locked_25_s),
|
|
.up_rst_done_out (up_ch_rst_done_25_s),
|
|
.up_prbserr_out (up_ch_prbserr_25_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_25_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_25_s));
|
|
|
|
assign up_ch_addr_25 = up_ch_addr;
|
|
assign up_ch_wr_25 = up_ch_wr;
|
|
assign up_ch_wdata_25 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (25),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_25 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_25),
|
|
.up_rdata_in (up_ch_rdata_24_s),
|
|
.up_ready_in (up_ch_ready_24_s),
|
|
.up_rdata (up_ch_rdata_25),
|
|
.up_ready (up_ch_ready_25),
|
|
.up_rdata_out (up_ch_rdata_25_s),
|
|
.up_ready_out (up_ch_ready_25_s));
|
|
|
|
assign up_es_addr_26 = up_es_addr;
|
|
assign up_es_wr_26 = up_es_wr;
|
|
assign up_es_wdata_26 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (26),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_26 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_26),
|
|
.up_rdata_in (up_es_rdata_25_s),
|
|
.up_ready_in (up_es_ready_25_s),
|
|
.up_rdata (up_es_rdata_26),
|
|
.up_ready (up_es_ready_26),
|
|
.up_rdata_out (up_es_rdata_26_s),
|
|
.up_ready_out (up_es_ready_26_s));
|
|
|
|
assign up_ch_rst_26 = up_ch_rst;
|
|
assign up_ch_user_ready_26 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_26 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_26 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_26 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_26 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_26 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_26 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_26 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_26 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_26 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_26 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_26 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (26),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_26 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_25_s),
|
|
.up_rst_done_in (up_ch_rst_done_25_s),
|
|
.up_prbserr_in (up_ch_prbserr_25_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_25_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_25_s),
|
|
.up_pll_locked (up_ch_pll_locked_26),
|
|
.up_rst_done (up_ch_rst_done_26),
|
|
.up_prbserr (up_ch_prbserr_26),
|
|
.up_prbslocked (up_ch_prbslocked_26),
|
|
.up_bufstatus (up_ch_bufstatus_26),
|
|
.up_pll_locked_out (up_ch_pll_locked_26_s),
|
|
.up_rst_done_out (up_ch_rst_done_26_s),
|
|
.up_prbserr_out (up_ch_prbserr_26_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_26_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_26_s));
|
|
|
|
assign up_ch_addr_26 = up_ch_addr;
|
|
assign up_ch_wr_26 = up_ch_wr;
|
|
assign up_ch_wdata_26 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (26),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_26 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_26),
|
|
.up_rdata_in (up_ch_rdata_25_s),
|
|
.up_ready_in (up_ch_ready_25_s),
|
|
.up_rdata (up_ch_rdata_26),
|
|
.up_ready (up_ch_ready_26),
|
|
.up_rdata_out (up_ch_rdata_26_s),
|
|
.up_ready_out (up_ch_ready_26_s));
|
|
|
|
assign up_es_addr_27 = up_es_addr;
|
|
assign up_es_wr_27 = up_es_wr;
|
|
assign up_es_wdata_27 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (27),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_27 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_27),
|
|
.up_rdata_in (up_es_rdata_26_s),
|
|
.up_ready_in (up_es_ready_26_s),
|
|
.up_rdata (up_es_rdata_27),
|
|
.up_ready (up_es_ready_27),
|
|
.up_rdata_out (up_es_rdata_27_s),
|
|
.up_ready_out (up_es_ready_27_s));
|
|
|
|
assign up_ch_rst_27 = up_ch_rst;
|
|
assign up_ch_user_ready_27 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_27 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_27 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_27 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_27 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_27 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_27 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_27 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_27 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_27 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_27 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_27 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (27),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_27 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_26_s),
|
|
.up_rst_done_in (up_ch_rst_done_26_s),
|
|
.up_prbserr_in (up_ch_prbserr_26_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_26_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_26_s),
|
|
.up_pll_locked (up_ch_pll_locked_27),
|
|
.up_rst_done (up_ch_rst_done_27),
|
|
.up_prbserr (up_ch_prbserr_27),
|
|
.up_prbslocked (up_ch_prbslocked_27),
|
|
.up_bufstatus (up_ch_bufstatus_27),
|
|
.up_pll_locked_out (up_ch_pll_locked_27_s),
|
|
.up_rst_done_out (up_ch_rst_done_27_s),
|
|
.up_prbserr_out (up_ch_prbserr_27_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_27_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_27_s));
|
|
|
|
assign up_ch_addr_27 = up_ch_addr;
|
|
assign up_ch_wr_27 = up_ch_wr;
|
|
assign up_ch_wdata_27 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (27),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_27 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_27),
|
|
.up_rdata_in (up_ch_rdata_26_s),
|
|
.up_ready_in (up_ch_ready_26_s),
|
|
.up_rdata (up_ch_rdata_27),
|
|
.up_ready (up_ch_ready_27),
|
|
.up_rdata_out (up_ch_rdata_27_s),
|
|
.up_ready_out (up_ch_ready_27_s));
|
|
|
|
assign up_cm_addr_28 = up_cm_addr;
|
|
assign up_cm_wr_28 = up_cm_wr;
|
|
assign up_cm_wdata_28 = up_cm_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (28),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_cm_28 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_cm_sel),
|
|
.up_enb (up_cm_enb),
|
|
.up_enb_out (up_cm_enb_28),
|
|
.up_rdata_in (up_cm_rdata_24_s),
|
|
.up_ready_in (up_cm_ready_24_s),
|
|
.up_rdata (up_cm_rdata_28),
|
|
.up_ready (up_cm_ready_28),
|
|
.up_rdata_out (up_cm_rdata_28_s),
|
|
.up_ready_out (up_cm_ready_28_s));
|
|
|
|
assign up_es_addr_28 = up_es_addr;
|
|
assign up_es_wr_28 = up_es_wr;
|
|
assign up_es_wdata_28 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (28),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_28 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_28),
|
|
.up_rdata_in (up_es_rdata_27_s),
|
|
.up_ready_in (up_es_ready_27_s),
|
|
.up_rdata (up_es_rdata_28),
|
|
.up_ready (up_es_ready_28),
|
|
.up_rdata_out (up_es_rdata_28_s),
|
|
.up_ready_out (up_es_ready_28_s));
|
|
|
|
assign up_ch_rst_28 = up_ch_rst;
|
|
assign up_ch_user_ready_28 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_28 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_28 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_28 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_28 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_28 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_28 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_28 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_28 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_28 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_28 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_28 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (28),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_28 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_27_s),
|
|
.up_rst_done_in (up_ch_rst_done_27_s),
|
|
.up_prbserr_in (up_ch_prbserr_27_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_27_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_27_s),
|
|
.up_pll_locked (up_ch_pll_locked_28),
|
|
.up_rst_done (up_ch_rst_done_28),
|
|
.up_prbserr (up_ch_prbserr_28),
|
|
.up_prbslocked (up_ch_prbslocked_28),
|
|
.up_bufstatus (up_ch_bufstatus_28),
|
|
.up_pll_locked_out (up_ch_pll_locked_28_s),
|
|
.up_rst_done_out (up_ch_rst_done_28_s),
|
|
.up_prbserr_out (up_ch_prbserr_28_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_28_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_28_s));
|
|
|
|
assign up_ch_addr_28 = up_ch_addr;
|
|
assign up_ch_wr_28 = up_ch_wr;
|
|
assign up_ch_wdata_28 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (28),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_28 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_28),
|
|
.up_rdata_in (up_ch_rdata_27_s),
|
|
.up_ready_in (up_ch_ready_27_s),
|
|
.up_rdata (up_ch_rdata_28),
|
|
.up_ready (up_ch_ready_28),
|
|
.up_rdata_out (up_ch_rdata_28_s),
|
|
.up_ready_out (up_ch_ready_28_s));
|
|
|
|
assign up_es_addr_29 = up_es_addr;
|
|
assign up_es_wr_29 = up_es_wr;
|
|
assign up_es_wdata_29 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (29),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_29 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_29),
|
|
.up_rdata_in (up_es_rdata_28_s),
|
|
.up_ready_in (up_es_ready_28_s),
|
|
.up_rdata (up_es_rdata_29),
|
|
.up_ready (up_es_ready_29),
|
|
.up_rdata_out (up_es_rdata_29_s),
|
|
.up_ready_out (up_es_ready_29_s));
|
|
|
|
assign up_ch_rst_29 = up_ch_rst;
|
|
assign up_ch_user_ready_29 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_29 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_29 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_29 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_29 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_29 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_29 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_29 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_29 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_29 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_29 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_29 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (29),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_29 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_28_s),
|
|
.up_rst_done_in (up_ch_rst_done_28_s),
|
|
.up_prbserr_in (up_ch_prbserr_28_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_28_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_28_s),
|
|
.up_pll_locked (up_ch_pll_locked_29),
|
|
.up_rst_done (up_ch_rst_done_29),
|
|
.up_prbserr (up_ch_prbserr_29),
|
|
.up_prbslocked (up_ch_prbslocked_29),
|
|
.up_bufstatus (up_ch_bufstatus_29),
|
|
.up_pll_locked_out (up_ch_pll_locked_29_s),
|
|
.up_rst_done_out (up_ch_rst_done_29_s),
|
|
.up_prbserr_out (up_ch_prbserr_29_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_29_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_29_s));
|
|
|
|
assign up_ch_addr_29 = up_ch_addr;
|
|
assign up_ch_wr_29 = up_ch_wr;
|
|
assign up_ch_wdata_29 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (29),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_29 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_29),
|
|
.up_rdata_in (up_ch_rdata_28_s),
|
|
.up_ready_in (up_ch_ready_28_s),
|
|
.up_rdata (up_ch_rdata_29),
|
|
.up_ready (up_ch_ready_29),
|
|
.up_rdata_out (up_ch_rdata_29_s),
|
|
.up_ready_out (up_ch_ready_29_s));
|
|
|
|
assign up_es_addr_30 = up_es_addr;
|
|
assign up_es_wr_30 = up_es_wr;
|
|
assign up_es_wdata_30 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (30),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_30 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_30),
|
|
.up_rdata_in (up_es_rdata_29_s),
|
|
.up_ready_in (up_es_ready_29_s),
|
|
.up_rdata (up_es_rdata_30),
|
|
.up_ready (up_es_ready_30),
|
|
.up_rdata_out (up_es_rdata_30_s),
|
|
.up_ready_out (up_es_ready_30_s));
|
|
|
|
assign up_ch_rst_30 = up_ch_rst;
|
|
assign up_ch_user_ready_30 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_30 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_30 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_30 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_30 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_30 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_30 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_30 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_30 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_30 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_30 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_30 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (30),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_30 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_29_s),
|
|
.up_rst_done_in (up_ch_rst_done_29_s),
|
|
.up_prbserr_in (up_ch_prbserr_29_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_29_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_29_s),
|
|
.up_pll_locked (up_ch_pll_locked_30),
|
|
.up_rst_done (up_ch_rst_done_30),
|
|
.up_prbserr (up_ch_prbserr_30),
|
|
.up_prbslocked (up_ch_prbslocked_30),
|
|
.up_bufstatus (up_ch_bufstatus_30),
|
|
.up_pll_locked_out (up_ch_pll_locked_30_s),
|
|
.up_rst_done_out (up_ch_rst_done_30_s),
|
|
.up_prbserr_out (up_ch_prbserr_30_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_30_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_30_s));
|
|
|
|
assign up_ch_addr_30 = up_ch_addr;
|
|
assign up_ch_wr_30 = up_ch_wr;
|
|
assign up_ch_wdata_30 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (30),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_30 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_30),
|
|
.up_rdata_in (up_ch_rdata_29_s),
|
|
.up_ready_in (up_ch_ready_29_s),
|
|
.up_rdata (up_ch_rdata_30),
|
|
.up_ready (up_ch_ready_30),
|
|
.up_rdata_out (up_ch_rdata_30_s),
|
|
.up_ready_out (up_ch_ready_30_s));
|
|
|
|
assign up_es_addr_31 = up_es_addr;
|
|
assign up_es_wr_31 = up_es_wr;
|
|
assign up_es_wdata_31 = up_es_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (31),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_es_31 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_es_sel),
|
|
.up_enb (up_es_enb),
|
|
.up_enb_out (up_es_enb_31),
|
|
.up_rdata_in (up_es_rdata_30_s),
|
|
.up_ready_in (up_es_ready_30_s),
|
|
.up_rdata (up_es_rdata_31),
|
|
.up_ready (up_es_ready_31),
|
|
.up_rdata_out (up_es_rdata_31_s),
|
|
.up_ready_out (up_es_ready_31_s));
|
|
|
|
assign up_ch_rst_31 = up_ch_rst;
|
|
assign up_ch_user_ready_31 = up_ch_user_ready;
|
|
assign up_ch_lpm_dfe_n_31 = up_ch_lpm_dfe_n;
|
|
assign up_ch_rate_31 = up_ch_rate;
|
|
assign up_ch_sys_clk_sel_31 = up_ch_sys_clk_sel;
|
|
assign up_ch_out_clk_sel_31 = up_ch_out_clk_sel;
|
|
assign up_ch_tx_diffctrl_31 = up_ch_tx_diffctrl;
|
|
assign up_ch_tx_postcursor_31 = up_ch_tx_postcursor;
|
|
assign up_ch_tx_precursor_31 = up_ch_tx_precursor;
|
|
assign up_ch_prbsforceerr_31 = up_ch_prbsforceerr;
|
|
assign up_ch_prbssel_31 = up_ch_prbssel;
|
|
assign up_ch_prbscntreset_31 = up_ch_prbscntreset;
|
|
assign up_ch_bufstatus_rst_31 = up_ch_bufstatus_rst;
|
|
|
|
axi_adxcvr_mstatus #(
|
|
.XCVR_ID (31),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mstatus_ch_31 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_pll_locked_in (up_ch_pll_locked_30_s),
|
|
.up_rst_done_in (up_ch_rst_done_30_s),
|
|
.up_prbserr_in (up_ch_prbserr_30_s),
|
|
.up_prbslocked_in (up_ch_prbslocked_30_s),
|
|
.up_bufstatus_in (up_ch_bufstatus_30_s),
|
|
.up_pll_locked (up_ch_pll_locked_31),
|
|
.up_rst_done (up_ch_rst_done_31),
|
|
.up_prbserr (up_ch_prbserr_31),
|
|
.up_prbslocked (up_ch_prbslocked_31),
|
|
.up_bufstatus (up_ch_bufstatus_31),
|
|
.up_pll_locked_out (up_ch_pll_locked_31_s),
|
|
.up_rst_done_out (up_ch_rst_done_31_s),
|
|
.up_prbserr_out (up_ch_prbserr_31_s),
|
|
.up_prbslocked_out (up_ch_prbslocked_31_s),
|
|
.up_bufstatus_out (up_ch_bufstatus_31_s));
|
|
|
|
assign up_ch_addr_31 = up_ch_addr;
|
|
assign up_ch_wr_31 = up_ch_wr;
|
|
assign up_ch_wdata_31 = up_ch_wdata;
|
|
|
|
axi_adxcvr_mdrp #(
|
|
.XCVR_ID (31),
|
|
.NUM_OF_LANES (NUM_OF_LANES)
|
|
) i_mdrp_ch_31 (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_ch_sel),
|
|
.up_enb (up_ch_enb),
|
|
.up_enb_out (up_ch_enb_31),
|
|
.up_rdata_in (up_ch_rdata_30_s),
|
|
.up_ready_in (up_ch_ready_30_s),
|
|
.up_rdata (up_ch_rdata_31),
|
|
.up_ready (up_ch_ready_31),
|
|
.up_rdata_out (up_ch_rdata_31_s),
|
|
.up_ready_out (up_ch_ready_31_s));
|
|
|
|
axi_adxcvr_es #(
|
|
.XCVR_TYPE (XCVR_TYPE),
|
|
.TX_OR_RX_N (TX_OR_RX_N)
|
|
) i_es (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_es_enb (up_es_enb),
|
|
.up_es_addr (up_es_addr),
|
|
.up_es_wr (up_es_wr),
|
|
.up_es_wdata (up_es_wdata),
|
|
.up_es_rdata (up_es_rdata_15_s),
|
|
.up_es_ready (up_es_ready_15_s),
|
|
.up_ch_lpm_dfe_n (up_ch_lpm_dfe_n),
|
|
.up_es_req (up_es_req),
|
|
.up_es_ack (up_es_ack),
|
|
.up_es_pscale (up_es_pscale),
|
|
.up_es_vrange (up_es_vrange),
|
|
.up_es_vstep (up_es_vstep),
|
|
.up_es_vmax (up_es_vmax),
|
|
.up_es_vmin (up_es_vmin),
|
|
.up_es_hmax (up_es_hmax),
|
|
.up_es_hmin (up_es_hmin),
|
|
.up_es_hstep (up_es_hstep),
|
|
.up_es_saddr (up_es_saddr),
|
|
.up_es_status (up_es_status),
|
|
.up_axi_awvalid (m_axi_awvalid),
|
|
.up_axi_awaddr (m_axi_awaddr),
|
|
.up_axi_awprot (m_axi_awprot),
|
|
.up_axi_awready (m_axi_awready),
|
|
.up_axi_wvalid (m_axi_wvalid),
|
|
.up_axi_wdata (m_axi_wdata),
|
|
.up_axi_wstrb (m_axi_wstrb),
|
|
.up_axi_wready (m_axi_wready),
|
|
.up_axi_bvalid (m_axi_bvalid),
|
|
.up_axi_bresp (m_axi_bresp),
|
|
.up_axi_bready (m_axi_bready),
|
|
.up_axi_arvalid (m_axi_arvalid),
|
|
.up_axi_araddr (m_axi_araddr),
|
|
.up_axi_arprot (m_axi_arprot),
|
|
.up_axi_arready (m_axi_arready),
|
|
.up_axi_rvalid (m_axi_rvalid),
|
|
.up_axi_rdata (m_axi_rdata),
|
|
.up_axi_rresp (m_axi_rresp),
|
|
.up_axi_rready (m_axi_rready));
|
|
|
|
axi_adxcvr_up #(
|
|
.ID (ID),
|
|
.LINK_MODE (LINK_MODE),
|
|
.NUM_OF_LANES (NUM_OF_LANES),
|
|
.XCVR_TYPE (XCVR_TYPE),
|
|
.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
|
|
.FPGA_FAMILY(FPGA_FAMILY),
|
|
.SPEED_GRADE(SPEED_GRADE),
|
|
.DEV_PACKAGE(DEV_PACKAGE),
|
|
.FPGA_VOLTAGE(FPGA_VOLTAGE),
|
|
.TX_OR_RX_N (TX_OR_RX_N),
|
|
.QPLL_ENABLE (QPLL_ENABLE),
|
|
.LPM_OR_DFE_N (LPM_OR_DFE_N),
|
|
.RATE (RATE),
|
|
.TX_DIFFCTRL (TX_DIFFCTRL),
|
|
.TX_POSTCURSOR (TX_POSTCURSOR),
|
|
.TX_PRECURSOR (TX_PRECURSOR),
|
|
.SYS_CLK_SEL (SYS_CLK_SEL),
|
|
.OUT_CLK_SEL (OUT_CLK_SEL)
|
|
) i_up (
|
|
.up_cm_sel (up_cm_sel),
|
|
.up_cm_enb (up_cm_enb),
|
|
.up_cm_addr (up_cm_addr),
|
|
.up_cm_wr (up_cm_wr),
|
|
.up_cm_wdata (up_cm_wdata),
|
|
.up_cm_rdata (up_cm_rdata_12_s),
|
|
.up_cm_ready (up_cm_ready_12_s),
|
|
.up_ch_pll_locked (up_ch_pll_locked_15_s),
|
|
.up_ch_rst (up_ch_rst),
|
|
.up_ch_user_ready (up_ch_user_ready),
|
|
.up_ch_rst_done (up_ch_rst_done_15_s),
|
|
.up_ch_prbsforceerr (up_ch_prbsforceerr),
|
|
.up_ch_prbssel (up_ch_prbssel),
|
|
.up_ch_prbscntreset (up_ch_prbscntreset),
|
|
.up_ch_prbserr (up_ch_prbserr_15_s),
|
|
.up_ch_prbslocked (up_ch_prbslocked_15_s),
|
|
.up_ch_bufstatus (up_ch_bufstatus_15_s),
|
|
.up_ch_bufstatus_rst (up_ch_bufstatus_rst),
|
|
.up_ch_lpm_dfe_n (up_ch_lpm_dfe_n),
|
|
.up_ch_rate (up_ch_rate),
|
|
.up_ch_sys_clk_sel (up_ch_sys_clk_sel),
|
|
.up_ch_out_clk_sel (up_ch_out_clk_sel),
|
|
.up_ch_tx_diffctrl (up_ch_tx_diffctrl),
|
|
.up_ch_tx_postcursor (up_ch_tx_postcursor),
|
|
.up_ch_tx_precursor (up_ch_tx_precursor),
|
|
.up_ch_sel (up_ch_sel),
|
|
.up_ch_enb (up_ch_enb),
|
|
.up_ch_addr (up_ch_addr),
|
|
.up_ch_wr (up_ch_wr),
|
|
.up_ch_wdata (up_ch_wdata),
|
|
.up_ch_rdata (up_ch_rdata_15_s),
|
|
.up_ch_ready (up_ch_ready_15_s),
|
|
.up_es_sel (up_es_sel),
|
|
.up_es_req (up_es_req),
|
|
.up_es_ack (up_es_ack),
|
|
.up_es_reset (up_es_reset),
|
|
.up_es_pscale (up_es_pscale),
|
|
.up_es_vrange (up_es_vrange),
|
|
.up_es_vstep (up_es_vstep),
|
|
.up_es_vmax (up_es_vmax),
|
|
.up_es_vmin (up_es_vmin),
|
|
.up_es_hmax (up_es_hmax),
|
|
.up_es_hmin (up_es_hmin),
|
|
.up_es_hstep (up_es_hstep),
|
|
.up_es_saddr (up_es_saddr),
|
|
.up_es_status (up_es_status),
|
|
.up_status (up_status),
|
|
.up_pll_rst (up_pll_rst),
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_wreq (up_wreq),
|
|
.up_waddr (up_waddr),
|
|
.up_wdata (up_wdata),
|
|
.up_wack (up_wack),
|
|
.up_rreq (up_rreq),
|
|
.up_raddr (up_raddr),
|
|
.up_rdata (up_rdata),
|
|
.up_rack (up_rack));
|
|
|
|
up_axi #(
|
|
.AXI_ADDRESS_WIDTH (12)
|
|
) i_axi (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_axi_awvalid (s_axi_awvalid),
|
|
.up_axi_awaddr (s_axi_awaddr),
|
|
.up_axi_awready (s_axi_awready),
|
|
.up_axi_wvalid (s_axi_wvalid),
|
|
.up_axi_wdata (s_axi_wdata),
|
|
.up_axi_wstrb (s_axi_wstrb),
|
|
.up_axi_wready (s_axi_wready),
|
|
.up_axi_bvalid (s_axi_bvalid),
|
|
.up_axi_bresp (s_axi_bresp),
|
|
.up_axi_bready (s_axi_bready),
|
|
.up_axi_arvalid (s_axi_arvalid),
|
|
.up_axi_araddr (s_axi_araddr),
|
|
.up_axi_arready (s_axi_arready),
|
|
.up_axi_rvalid (s_axi_rvalid),
|
|
.up_axi_rresp (s_axi_rresp),
|
|
.up_axi_rdata (s_axi_rdata),
|
|
.up_axi_rready (s_axi_rready),
|
|
.up_wreq (up_wreq),
|
|
.up_waddr (up_waddr),
|
|
.up_wdata (up_wdata),
|
|
.up_wack (up_wack),
|
|
.up_rreq (up_rreq),
|
|
.up_raddr (up_raddr),
|
|
.up_rdata (up_rdata),
|
|
.up_rack (up_rack));
|
|
|
|
endmodule
|