338 lines
12 KiB
Verilog
338 lines
12 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ps/1ps
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module ad_serdes_in #(
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parameter FPGA_TECHNOLOGY = 0,
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parameter CMOS_LVDS_N = 0,
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parameter DDR_OR_SDR_N = 0,
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parameter SERDES_FACTOR = 8,
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parameter DATA_WIDTH = 16,
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parameter DRP_WIDTH = 5,
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parameter IODELAY_ENABLE = 1,
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parameter IODELAY_CTRL = 0,
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parameter IODELAY_GROUP = "dev_if_delay_group",
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parameter REFCLK_FREQUENCY = 200
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) (
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// reset and clocks
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input rst,
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input clk,
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input div_clk,
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// data interface
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output [(DATA_WIDTH-1):0] data_s0, // last bit received
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output [(DATA_WIDTH-1):0] data_s1,
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output [(DATA_WIDTH-1):0] data_s2,
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output [(DATA_WIDTH-1):0] data_s3,
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output [(DATA_WIDTH-1):0] data_s4,
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output [(DATA_WIDTH-1):0] data_s5,
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output [(DATA_WIDTH-1):0] data_s6,
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output [(DATA_WIDTH-1):0] data_s7, // 1st bit received
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input [(DATA_WIDTH-1):0] data_in_p,
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input [(DATA_WIDTH-1):0] data_in_n,
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// delay-data interface
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input up_clk,
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input [(DATA_WIDTH-1):0] up_dld,
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input [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata,
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output [((DATA_WIDTH*DRP_WIDTH)-1):0] up_drdata,
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// delay-control interface
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input delay_clk,
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input delay_rst,
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output delay_locked
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);
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localparam SEVEN_SERIES = 1;
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localparam ULTRASCALE = 2;
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localparam ULTRASCALE_PLUS = 3;
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localparam DATA_RATE = (DDR_OR_SDR_N) ? "DDR" : "SDR";
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localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0;
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localparam SIM_DEVICE = FPGA_TECHNOLOGY == SEVEN_SERIES ? "7SERIES" :
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FPGA_TECHNOLOGY == ULTRASCALE ? "ULTRASCALE" :
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FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE_PLUS" :
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"UNSUPPORTED";
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// when ULTRASCALE_PLUS, use ULTRASCALE because IDELAYCTRL is the same for both
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// and doesn't know ULTRASCALE_PLUS string
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localparam SIM_DEVICE_IDELAYCTRL = FPGA_TECHNOLOGY == SEVEN_SERIES ? "7SERIES" :
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FPGA_TECHNOLOGY == ULTRASCALE ? "ULTRASCALE" :
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FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE" :
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"UNSUPPORTED";
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// internal registers
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reg [6:0] serdes_rst_seq;
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// internal signals
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wire [(DATA_WIDTH-1):0] data_in_ibuf_s;
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wire [(DATA_WIDTH-1):0] data_in_idelay_s;
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wire [(DATA_WIDTH-1):0] data_shift1_s;
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wire [(DATA_WIDTH-1):0] data_shift2_s;
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wire serdes_rst = serdes_rst_seq[6];
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// delay controller
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generate
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if (IODELAY_CTRL_ENABLED == 1) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYCTRL #(
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.SIM_DEVICE(SIM_DEVICE_IDELAYCTRL)
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) i_delay_ctrl (
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.RST (delay_rst),
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.REFCLK (delay_clk),
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.RDY (delay_locked));
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end else begin
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assign delay_locked = 1'b1;
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end
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endgenerate
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// received data interface: ibuf -> idelay -> iserdes
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// ibuf
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genvar l_inst;
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generate
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for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_io
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if (CMOS_LVDS_N == 0) begin
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IBUFDS i_ibuf (
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.I (data_in_p[l_inst]),
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.IB (data_in_n[l_inst]),
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.O (data_in_ibuf_s[l_inst]));
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end else begin
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IBUF i_ibuf (
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.I (data_in_p[l_inst]),
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.O (data_in_ibuf_s[l_inst]));
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end
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end
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endgenerate
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// bypass IDELAY
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generate
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if (IODELAY_ENABLE == 0) begin
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assign data_in_idelay_s = data_in_ibuf_s;
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end
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endgenerate
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always @ (posedge div_clk) begin
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if (rst) begin
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serdes_rst_seq [6:0] <= 7'b0001110;
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end else begin
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serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0};
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end
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end
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// idelay + iserdes
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generate
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if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
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for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
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if (IODELAY_ENABLE == 1) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("IDATAIN"),
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.HIGH_PERFORMANCE_MODE ("FALSE"),
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.IDELAY_TYPE ("VAR_LOAD"),
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.IDELAY_VALUE (0),
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.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
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.PIPE_SEL ("FALSE"),
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.SIGNAL_PATTERN ("DATA")
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) i_idelay (
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.CE (1'b0),
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.INC (1'b0),
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.DATAIN (1'b0),
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.LDPIPEEN (1'b0),
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.CINVCTRL (1'b0),
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.REGRST (1'b0),
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.C (up_clk),
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.IDATAIN (data_in_ibuf_s[l_inst]),
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.DATAOUT (data_in_idelay_s[l_inst]),
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.LD (up_dld[l_inst]),
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.CNTVALUEIN (up_dwdata[DRP_WIDTH*l_inst +: DRP_WIDTH]),
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.CNTVALUEOUT (up_drdata[DRP_WIDTH*l_inst +: DRP_WIDTH]));
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end
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ISERDESE2 #(
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.DATA_RATE (DATA_RATE),
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.DATA_WIDTH (SERDES_FACTOR),
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.DYN_CLKDIV_INV_EN ("FALSE"),
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.DYN_CLK_INV_EN ("FALSE"),
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.INIT_Q1 (1'b0),
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.INIT_Q2 (1'b0),
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.INIT_Q3 (1'b0),
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.INIT_Q4 (1'b0),
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.INTERFACE_TYPE ("NETWORKING"),
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.IOBDELAY ("IFD"),
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.NUM_CE (2),
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.OFB_USED ("FALSE"),
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.SERDES_MODE ("MASTER"),
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.SRVAL_Q1 (1'b0),
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.SRVAL_Q2 (1'b0),
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.SRVAL_Q3 (1'b0),
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.SRVAL_Q4 (1'b0)
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) i_iserdes (
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.O (),
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.Q1 (data_s0[l_inst]),
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.Q2 (data_s1[l_inst]),
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.Q3 (data_s2[l_inst]),
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.Q4 (data_s3[l_inst]),
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.Q5 (data_s4[l_inst]),
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.Q6 (data_s5[l_inst]),
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.Q7 (data_s6[l_inst]),
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.Q8 (data_s7[l_inst]),
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.SHIFTOUT1 (),
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.SHIFTOUT2 (),
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.BITSLIP (1'b0),
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.CE1 (1'b1),
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.CE2 (1'b1),
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.CLKDIVP (1'b0),
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.CLK (clk),
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.CLKB (~clk),
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.CLKDIV (div_clk),
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.OCLK (1'b0),
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.DYNCLKDIVSEL (1'b0),
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.DYNCLKSEL (1'b0),
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.D (1'b0),
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.DDLY (data_in_idelay_s[l_inst]),
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.OFB (1'b0),
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.OCLKB (1'b0),
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.RST (serdes_rst),
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.SHIFTIN1 (1'b0),
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.SHIFTIN2 (1'b0));
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end /* g_data */
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end
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endgenerate
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generate
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if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
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for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
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wire div_dld;
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wire en_vtc;
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wire ld_cnt;
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reg [4:0] vtc_cnt = {5{1'b1}};
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sync_event sync_load (
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.in_clk (up_clk),
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.in_event (up_dld[l_inst]),
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.out_clk (div_clk),
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.out_event (div_dld));
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if (IODELAY_ENABLE == 1) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYE3 #(
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.CASCADE ("NONE"), // Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
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.DELAY_FORMAT ("TIME"), // Units of the DELAY_VALUE (COUNT, TIME)
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.DELAY_SRC ("IDATAIN"), // Delay input (DATAIN, IDATAIN)
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.DELAY_TYPE ("VAR_LOAD"), // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
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.DELAY_VALUE (0), // Input delay value setting
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.IS_CLK_INVERTED (1'b0), // Optional inversion for CLK
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.IS_RST_INVERTED (1'b0), // Optional inversion for RST
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.REFCLK_FREQUENCY (500.0), // IDELAYCTRL clock input frequency in MHz (200.0-2667.0)
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.SIM_DEVICE (SIM_DEVICE), // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
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// ULTRASCALE_PLUS_ES2)
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.UPDATE_MODE ("ASYNC") // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
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) i_idelay (
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.CASC_OUT (), // 1-bit output: Cascade delay output to ODELAY input cascade
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.CNTVALUEOUT (up_drdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), // 9-bit output: Counter value output
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.DATAOUT (data_in_idelay_s[l_inst]), // 1-bit output: Delayed data output
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.CASC_IN (1'b0), // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
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.CASC_RETURN (1'b0), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
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.CE (1'b0), // 1-bit input: Active high enable increment/decrement input
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.CLK (div_clk), // 1-bit input: Clock input
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.CNTVALUEIN (up_dwdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), // 9-bit input: Counter value input
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.DATAIN (1'b0), // 1-bit input: Data input from the logic
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.EN_VTC (en_vtc), // 1-bit input: Keep delay constant over VT
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.IDATAIN (data_in_ibuf_s[l_inst]), // 1-bit input: Data input from the IOBUF
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.INC (1'b0), // 1-bit input: Increment / Decrement tap delay input
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.LOAD (ld_cnt), // 1-bit input: Load DELAY_VALUE input
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.RST (rst)); // 1-bit input: Asynchronous Reset to the DELAY_VALUE
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end
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always @(posedge div_clk) begin
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if (div_dld) begin
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vtc_cnt <= 'h0;
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end else if (~(&vtc_cnt)) begin
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vtc_cnt <= vtc_cnt + 1;
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end
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end
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assign en_vtc = &vtc_cnt;
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assign ld_cnt = ~vtc_cnt[4] & (&vtc_cnt[3:0]);
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ISERDESE3 #(
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.DATA_WIDTH (8), // Parallel data width (4,8)
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.FIFO_ENABLE ("FALSE"), // Enables the use of the FIFO
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.FIFO_SYNC_MODE ("FALSE"), // Enables the use of internal 2-stage synchronizers on the FIFO
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.IS_CLK_B_INVERTED (1'b0), // Optional inversion for CLK_B
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.IS_CLK_INVERTED (1'b0), // Optional inversion for CLK
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.IS_RST_INVERTED (1'b0), // Optional inversion for RST
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.SIM_DEVICE (SIM_DEVICE) // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
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// ULTRASCALE_PLUS_ES2)
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) i_iserdes(
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.FIFO_EMPTY (), // 1-bit output: FIFO empty flag
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.INTERNAL_DIVCLK (), // 1-bit output: Internally divided down clock used when FIFO is
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// disabled (do not connect)
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.Q ({data_s0[l_inst],
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data_s1[l_inst],
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data_s2[l_inst],
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data_s3[l_inst],
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data_s4[l_inst],
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data_s5[l_inst],
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data_s6[l_inst],
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data_s7[l_inst]}), // 8-bit registered output
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.CLK (clk), // 1-bit input: High-speed clock
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.CLKDIV (div_clk), // 1-bit input: Divided Clock
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.CLK_B (~clk), // 1-bit input: Inversion of High-speed clock CLK
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.D (data_in_idelay_s[l_inst]), // 1-bit input: Serial Data Input
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.FIFO_RD_CLK (div_clk), // 1-bit input: FIFO read clock
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.FIFO_RD_EN (1'b1), // 1-bit input: Enables reading the FIFO when asserted
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.RST (serdes_rst)); // 1-bit input: Asynchronous Reset
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end
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end
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endgenerate
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endmodule
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