259 lines
8.1 KiB
Verilog
259 lines
8.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module daq1_cpld (
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// FMC SPI interface
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input fmc_spi_sclk,
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input fmc_spi_csn,
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inout fmc_spi_sdio,
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output fmc_irq,
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// on board SPI interface
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output adc_spicsn,
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output dac_spicsn,
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output clk_spicsn,
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output sclk,
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inout sdio,
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// control and status lines
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input adc_fda,
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input adc_fdb,
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input adc_status_p,
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input adc_status_n,
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output adc_pwdn_stby,
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input dac_irqn,
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output dac_resetn,
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input clk_status1,
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input clk_status2,
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output clk_pwdnn,
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output clk_syncn,
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output clk_resetn
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);
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// FMC SPI Selects
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localparam [ 7:0] FMC_SPI_SEL_AD9684 = 8'h80;
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localparam [ 7:0] FMC_SPI_SEL_AD9122 = 8'h81;
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localparam [ 7:0] FMC_SPI_SEL_AD9523 = 8'h82;
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localparam [ 7:0] FMC_SPI_SEL_CPLD = 8'h83;
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// CPLD Register Map Addresses
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localparam [ 6:0] CPLD_VERSION_ADDR = 7'h00;
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localparam [ 6:0] ADC_CONTROL_ADDR = 7'h10;
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localparam [ 6:0] DAC_CONTROL_ADDR = 7'h11;
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localparam [ 6:0] CLK_CONTROL_ADDR = 7'h12;
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localparam [ 6:0] IRQ_MASK_ADDR = 7'h13;
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localparam [ 6:0] ADC_STATUS_ADDR = 7'h20;
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localparam [ 6:0] DAC_STATUS_ADDR = 7'h21;
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localparam [ 6:0] CLK_STATUS_ADDR = 7'h22;
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localparam [ 7:0] CPLD_VERSION = 8'h11;
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// Internal Registers/Signals
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reg [ 7:0] fmc_spi_dev_sel = 8'b0;
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reg [ 7:0] fmc_cpld_addr = 8'b0;
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reg [ 5:0] fmc_spi_counter = 6'b0;
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reg fmc_spi_csn_enb = 1'b1;
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reg [ 7:0] adc_control = 8'b0;
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reg [ 7:0] dac_control = 8'b0;
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reg [ 7:0] clk_control = 8'b0;
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reg [ 7:0] adc_status = 8'b0;
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reg [ 7:0] dac_status = 8'b0;
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reg [ 7:0] clk_status = 8'b0;
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reg cpld_to_fpga = 1'b0;
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reg [ 7:0] cpld_rdata = 8'b0;
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reg cpld_rdata_bit = 1'b0;
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reg [ 2:0] cpld_rdata_index = 3'h0;
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reg [ 7:0] cpld_wdata = 8'b0;
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reg [ 7:0] cpld_irq_mask = 8'b0;
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reg [ 7:0] cpld_irq = 8'b0;
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wire rdnwr;
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wire cpld_rdata_s;
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// SCLK counter for control signals
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always @(posedge fmc_spi_sclk or posedge fmc_spi_csn) begin
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if (fmc_spi_csn == 1'b1) begin
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fmc_spi_dev_sel <= 8'h0;
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fmc_cpld_addr <= 8'h0;
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end else begin
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if (fmc_spi_counter <= 7) begin
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fmc_spi_dev_sel <= {fmc_spi_dev_sel[6:0], fmc_spi_sdio};
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end
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if (fmc_spi_counter <= 15) begin
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fmc_cpld_addr <= {fmc_cpld_addr[6:0], fmc_spi_sdio};
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end
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end
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end
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// chip select control
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assign adc_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9684) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
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assign dac_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9122) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
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assign clk_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9523) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
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assign cpld_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_CPLD) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
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// SPI control and data
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assign sdio = cpld_to_fpga ? 1'bZ : fmc_spi_sdio;
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assign fmc_spi_sdio = cpld_to_fpga ? cpld_rdata_s : 1'bZ ;
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assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit;
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assign rdnwr = fmc_cpld_addr[7];
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assign sclk = (~(fmc_spi_csn | fmc_spi_csn_enb)) ? fmc_spi_sclk : 1'b0;
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always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
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if (fmc_spi_csn == 1'b1) begin
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fmc_spi_counter <= 6'h0;
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cpld_to_fpga <= 1'b0;
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fmc_spi_csn_enb <= 1'b1;
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end else begin
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fmc_spi_counter <= (fmc_spi_counter <= 6'h3F) ? fmc_spi_counter + 1 : fmc_spi_counter;
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fmc_spi_csn_enb <= (fmc_spi_counter < 7) ? 1'b1 : 1'b0;
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if (adc_spicsn & clk_spicsn) begin
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cpld_to_fpga <= (fmc_spi_counter >= 15) ? rdnwr : 1'b0;
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end else begin
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cpld_to_fpga <= (fmc_spi_counter >= 23) ? rdnwr : 1'b0;
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end
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end
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end
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// Internal register read access
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always @(fmc_cpld_addr) begin
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case (fmc_cpld_addr[6:0])
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CPLD_VERSION_ADDR :
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cpld_rdata <= CPLD_VERSION;
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ADC_CONTROL_ADDR :
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cpld_rdata <= adc_pwdn_stby;
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DAC_CONTROL_ADDR :
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cpld_rdata <= dac_resetn;
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CLK_CONTROL_ADDR :
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cpld_rdata <= {clk_syncn, clk_resetn, clk_pwdnn};
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IRQ_MASK_ADDR:
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cpld_rdata <= cpld_irq_mask;
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ADC_STATUS_ADDR :
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cpld_rdata <= {adc_status_p, adc_fdb, adc_fda};
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DAC_STATUS_ADDR :
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cpld_rdata <= dac_irqn;
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CLK_STATUS_ADDR :
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cpld_rdata <= {clk_status2, clk_status1};
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default:
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cpld_rdata <= 8'hFA;
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endcase
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end
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always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
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if (fmc_spi_csn == 1'b1) begin
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cpld_rdata_bit <= cpld_rdata[7];
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cpld_rdata_index <= 3'h6;
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end else begin
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if (cpld_to_fpga == 1'b1) begin
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cpld_rdata_bit <= cpld_rdata[cpld_rdata_index];
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cpld_rdata_index <= cpld_rdata_index - 1;
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end
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end
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end
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// Internal register write access
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always @(cpld_to_fpga, cpld_spicsn, fmc_spi_counter) begin
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if ((cpld_to_fpga == 1'b0) &&
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(cpld_spicsn == 1'b0) &&
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(fmc_spi_counter == 8'h18)) begin
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case (fmc_cpld_addr[6:0])
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ADC_CONTROL_ADDR :
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adc_control <= cpld_wdata;
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DAC_CONTROL_ADDR :
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dac_control <= cpld_wdata;
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CLK_CONTROL_ADDR :
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clk_control <= cpld_wdata;
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IRQ_MASK_ADDR:
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cpld_irq_mask <= cpld_wdata;
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endcase
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end
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end
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always @(posedge fmc_spi_sclk or posedge fmc_spi_csn) begin
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if (fmc_spi_csn == 1'b1) begin
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cpld_wdata <= 8'h0;
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end else begin
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if (fmc_spi_counter >= 16) begin
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cpld_wdata <= {cpld_wdata[6:0], fmc_spi_sdio};
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end
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end
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end
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// input/output logic
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// AD9648
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assign adc_pwdn_stby = adc_control[0];
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// AD9122
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assign dac_resetn = dac_control[0];
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// AD9523-1
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assign clk_pwdnn = clk_control[0];
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assign clk_resetn = clk_control[1];
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assign clk_syncn = clk_control[2];
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// interrupt logic
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always @(*) begin
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cpld_irq <= {2'b00, dac_irqn, clk_status2, clk_status1, adc_status_p, adc_fdb, adc_fda};
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end
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assign fmc_irq = |(~cpld_irq_mask & cpld_irq);
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endmodule
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