Sergiu Arpadi 297bed6721 ad7134_fmc: Change ODR signal to output ... FPGA is now generating the ODR signal using axi_pwm_gen. Both ADCs are now in slave mode.		2022-02-07 14:41:25 +02:00
..
Makefile	ad7134_fmc: Change ODR signal to output	2022-02-07 14:41:25 +02:00
system_bd.tcl	sysid: Upgrade framework, header/ip are now at 2/1.1.a	2021-01-20 01:02:56 +02:00
system_constr.xdc	ad7134_fmc/zed: Fix IO definitions for SDI lines	2019-11-27 10:04:37 +02:00
system_project.tcl	library: Move ad_iobuf to the common library, as it's not Xilinx specific	2020-11-02 16:13:35 +02:00
system_top.v	ad7134_fmc: Change ODR signal to output	2022-02-07 14:41:25 +02:00