Makefile
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all: Rename altera to intel
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2019-06-29 06:53:51 +03:00 |
axi_ad9684.v
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Add FPGA info parameters flow
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2019-03-30 11:26:11 +02:00 |
axi_ad9684_channel.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
axi_ad9684_constr.sdc
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ad9684- fix sdc typo
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2017-03-23 12:49:44 -04:00 |
axi_ad9684_constr.xdc
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axi_ad9684: Fix constraint file
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2016-02-12 14:38:59 +02:00 |
axi_ad9684_if.v
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Add FPGA info parameters flow
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2019-03-30 11:26:11 +02:00 |
axi_ad9684_pnmon.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |