122 lines
3.6 KiB
Verilog
122 lines
3.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module reset_manager_tb;
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parameter VCD_FILE = {`__FILE__,"cd"};
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`define TIMEOUT 1000000
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`include "tb_base.v"
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reg clk_a = 1'b0;
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reg clk_b = 1'b0;
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reg clk_c = 1'b0;
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reg [5:0] resetn_shift = 'h0;
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reg [10:0] counter = 'h00;
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reg ctrl_enable = 1'b0;
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reg ctrl_pause = 1'b0;
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always #10 clk_a <= ~clk_a;
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always #3 clk_b <= ~clk_b;
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always #7 clk_c <= ~clk_c;
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always @(posedge clk_a) begin
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counter <= counter + 1'b1;
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if (counter == 'h60 || counter == 'h150 || counter == 'h185) begin
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ctrl_enable <= 1'b1;
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end else if (counter == 'h100 || counter == 'h110 || counter == 'h180) begin
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ctrl_enable <= 1'b0;
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end
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if (counter == 'h160) begin
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ctrl_pause = 1'b1;
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end else if (counter == 'h190) begin
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ctrl_pause = 1'b0;
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end
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end
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reg [15:0] req_enabled_shift;
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wire req_enable;
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wire req_enabled = req_enabled_shift[15];
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reg [15:0] dest_enabled_shift;
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wire dest_enable;
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wire dest_enabled = dest_enabled_shift[15];
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reg [15:0] src_enabled_shift;
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wire src_enable;
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wire src_enabled = src_enabled_shift[15];
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always @(posedge clk_a) begin
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req_enabled_shift <= {req_enabled_shift[14:0],req_enable};
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end
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always @(posedge clk_b) begin
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dest_enabled_shift <= {dest_enabled_shift[14:0],dest_enable};
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end
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always @(posedge clk_c) begin
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src_enabled_shift <= {src_enabled_shift[14:0],src_enable};
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end
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axi_dmac_reset_manager i_reset_manager (
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.clk(clk_a),
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.resetn(resetn),
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.ctrl_pause(ctrl_pause),
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.ctrl_enable(ctrl_enable),
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.req_enable(req_enable),
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.req_enabled(req_enabled),
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.dest_clk(clk_b),
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.dest_ext_resetn(1'b0),
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.dest_enable(dest_enable),
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.dest_enabled(dest_enabled),
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.src_clk(clk_c),
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.src_ext_resetn(1'b0),
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.src_enable(src_enable),
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.src_enabled(src_enabled)
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);
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endmodule
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