490 lines
17 KiB
Verilog
Executable File
490 lines
17 KiB
Verilog
Executable File
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module loopback_tb;
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parameter VCD_FILE = "loopback_tb.vcd";
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parameter NUM_LANES = 4;
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parameter NUM_LINKS = 1;
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parameter OCTETS_PER_FRAME = 1;
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parameter FRAMES_PER_MULTIFRAME = 28;
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parameter NUM_CONVERTERS = 1;
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parameter N = 16;
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parameter NP = 16;
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parameter HIGH_DENSITY = 1'b0;
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parameter ENABLE_SCRAMBLER = 1;
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parameter BUFFER_EARLY_RELEASE = 1;
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parameter SYSREF_DISABLE = 0;
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parameter SYSREF_ONE_SHOT = 0;
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parameter LANE_DELAY = 1;
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parameter DATA_PATH_WIDTH = 4;
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parameter DATA_RANDOM = ENABLE_SCRAMBLER ? 0 : 1;
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localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
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localparam BEATS_PER_MULTIFRAME = OCTETS_PER_FRAME * FRAMES_PER_MULTIFRAME / 4;
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localparam TX_LATENCY = 4 + i_tx.NUM_OUTPUT_PIPELINE;
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wire [31:0] RX_LATENCY = 3 + i_rx.CHAR_INFO_REGISTERED + i_rx.ALIGN_MUX_REGISTERED + i_rx.SCRAMBLER_REGISTERED;
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wire [31:0] BASE_LATENCY = TX_LATENCY + RX_LATENCY;
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localparam SYSREF_HALF_COUNT = OCTETS_PER_FRAME * FRAMES_PER_MULTIFRAME;
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`define TIMEOUT 1000000
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`include "tb_base.v"
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reg [5:0] tx_counter = 'h00;
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reg [5:0] rx_counter = 'h00;
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reg [NUM_LANES*DATA_PATH_WIDTH*8-1:0] rx_mask = 64'hffffffffffff0000;
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wire tx_ready;
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wire rx_valid;
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wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] rx_data;
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wire [DATA_PATH_WIDTH-1:0] rx_eof;
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wire [DATA_PATH_WIDTH-1:0] rx_sof;
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reg data_mismatch = 1'b1;
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wire [NUM_LINKS-1:0] sync;
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always @(posedge clk) begin
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if (sync == 1'b0) begin
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tx_counter <= 'h00000000;
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end else if (tx_ready == 1'b1) begin
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tx_counter <= tx_counter + 1'b1;
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end
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end
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always @(posedge clk) begin
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if (sync == 1'b0) begin
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rx_counter <= 'h00000000;
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if (ENABLE_SCRAMBLER == 1'b1) begin
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rx_mask <= {NUM_LANES{64'hffffffffffff0000}}; // First two octets are invalid due to scrambling
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end else begin
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rx_mask <= {NUM_LANES{64'hffffffffffffffff}};
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end
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end else if (rx_valid == 1'b1) begin
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rx_counter <= rx_counter + 1'b1;
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rx_mask <= {NUM_LANES{64'hffffffffffffffff}};
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end
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end
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reg [(DATA_PATH_WIDTH*8)-1:0] tx_random_data;
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wire [(DATA_PATH_WIDTH*8)-1:0] tx_data;
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wire [(DATA_PATH_WIDTH*8)-1:0] rx_ref_data;
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genvar ii;
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generate
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for(ii = 0; ii < DATA_PATH_WIDTH; ii=ii+1) begin : data_gen
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wire [1:0] ii_sig = ii;
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always @(posedge clk) begin
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tx_random_data[ii*8+:8] <= $urandom();
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end
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assign tx_data[ii*8+:8] = DATA_RANDOM ? tx_random_data[ii*8+:8] : {tx_counter, ii_sig};
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assign rx_ref_data[ii*8+:8] = {rx_counter, ii_sig};
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end
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endgenerate
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wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] phy_data_out;
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wire [NUM_LANES*DATA_PATH_WIDTH-1:0] phy_charisk_out;
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wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] phy_data_in;
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wire [NUM_LANES*DATA_PATH_WIDTH-1:0] phy_charisk_in;
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reg [9:0] sysref_counter = 'h00;
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reg sysref_rx = 1'b0;
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reg sysref_tx = 1'b0;
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always @(posedge clk) begin
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if (sysref_counter == (SYSREF_HALF_COUNT-1)) begin
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sysref_rx <= ~sysref_rx;
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sysref_counter <= 'b0;
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end else begin
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sysref_counter <= sysref_counter + 1'b1;
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end
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sysref_tx <= sysref_rx;
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end
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localparam MAX_LANE_DELAY = LANE_DELAY + NUM_LANES;
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reg [10:0] phy_delay_fifo_wr;
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reg [DATA_PATH_WIDTH*9*NUM_LANES-1:0] phy_delay_fifo[0:MAX_LANE_DELAY-1];
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always @(posedge clk) begin
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phy_delay_fifo[phy_delay_fifo_wr] <= {phy_charisk_out,phy_data_out};
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if (reset == 1'b1 || phy_delay_fifo_wr == MAX_LANE_DELAY-1) begin
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phy_delay_fifo_wr <= 'h00;
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end else begin
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phy_delay_fifo_wr <= phy_delay_fifo_wr + 1'b1;
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end
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end
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genvar i;
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generate for (i = 0; i < NUM_LANES; i = i + 1) begin
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localparam OFF = MAX_LANE_DELAY - (i + LANE_DELAY);
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assign phy_data_in[DATA_PATH_WIDTH*8*i+(DATA_PATH_WIDTH*8)-1:DATA_PATH_WIDTH*8*i] =
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phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][DATA_PATH_WIDTH*8*i+(DATA_PATH_WIDTH*8)-1:DATA_PATH_WIDTH*8*i];
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assign phy_charisk_in[DATA_PATH_WIDTH*i+DATA_PATH_WIDTH-1:DATA_PATH_WIDTH*i] =
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phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][DATA_PATH_WIDTH*i+DATA_PATH_WIDTH-1+NUM_LANES*DATA_PATH_WIDTH*8:DATA_PATH_WIDTH*i+DATA_PATH_WIDTH*8*NUM_LANES];
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end endgenerate
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wire [NUM_LANES-1:0] tx_cfg_lanes_disable;
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wire [NUM_LINKS-1:0] tx_cfg_links_disable;
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wire [9:0] tx_cfg_octets_per_multiframe;
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wire [7:0] tx_cfg_octets_per_frame;
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wire [7:0] tx_device_cfg_lmfc_offset;
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wire [9:0] tx_device_cfg_octets_per_multiframe;
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wire [7:0] tx_device_cfg_octets_per_frame;
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wire [7:0] tx_device_cfg_beats_per_multiframe;
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wire tx_device_cfg_sysref_disable;
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wire tx_device_cfg_sysref_oneshot;
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wire tx_cfg_continuous_cgs;
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wire tx_cfg_continuous_ilas;
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wire tx_cfg_skip_ilas;
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wire [7:0] tx_cfg_mframes_per_ilas;
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wire tx_cfg_disable_char_replacement;
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wire tx_cfg_disable_scrambler;
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wire tx_lmfc_edge;
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wire tx_lmfc_clk;
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wire [DATA_PATH_WIDTH-1:0] tx_eof;
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wire [DATA_PATH_WIDTH-1:0] tx_sof;
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wire tx_ilas_config_rd;
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wire [1:0] tx_ilas_config_addr;
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wire [DATA_PATH_WIDTH*8*NUM_LANES-1:0] tx_ilas_config_data;
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wire tx_event_sysref_edge;
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wire tx_event_sysref_alignment_error;
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wire [NUM_LINKS-1:0] tx_status_sync;
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wire [1:0] tx_status_state;
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jesd204_tx_static_config #(
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS),
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.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
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.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME),
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.NUM_CONVERTERS(NUM_CONVERTERS),
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.N(N),
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.NP(NP),
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.HIGH_DENSITY(HIGH_DENSITY),
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.SCR(ENABLE_SCRAMBLER),
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.LINK_MODE(1),
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.SYSREF_DISABLE(SYSREF_DISABLE),
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.SYSREF_ONE_SHOT(SYSREF_ONE_SHOT),
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
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.TPL_DATA_PATH_WIDTH(DATA_PATH_WIDTH)
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) i_tx_cfg (
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.clk(clk),
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.cfg_lanes_disable(tx_cfg_lanes_disable),
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.cfg_links_disable(tx_cfg_links_disable),
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.cfg_octets_per_multiframe(tx_cfg_octets_per_multiframe),
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.cfg_octets_per_frame(tx_cfg_octets_per_frame),
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.cfg_continuous_cgs(tx_cfg_continuous_cgs),
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.cfg_continuous_ilas(tx_cfg_continuous_ilas),
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.cfg_skip_ilas(tx_cfg_skip_ilas),
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.cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas),
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.cfg_disable_char_replacement(tx_cfg_disable_char_replacement),
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.cfg_disable_scrambler(tx_cfg_disable_scrambler),
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.device_cfg_octets_per_multiframe(tx_device_cfg_octets_per_multiframe),
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.device_cfg_octets_per_frame(tx_device_cfg_octets_per_frame),
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.device_cfg_beats_per_multiframe(tx_device_cfg_beats_per_multiframe),
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.device_cfg_lmfc_offset(tx_device_cfg_lmfc_offset),
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.device_cfg_sysref_disable(tx_device_cfg_sysref_disable),
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.device_cfg_sysref_oneshot(tx_device_cfg_sysref_oneshot),
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.ilas_config_rd(tx_ilas_config_rd),
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.ilas_config_addr(tx_ilas_config_addr),
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.ilas_config_data(tx_ilas_config_data)
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);
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jesd204_tx #(
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS),
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.NUM_OUTPUT_PIPELINE(0),
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.LINK_MODE(1),
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
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.TPL_DATA_PATH_WIDTH(DATA_PATH_WIDTH),
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.ASYNC_CLK(0),
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.ENABLE_CHAR_REPLACE(1)
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) i_tx (
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.clk(clk),
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.reset(reset),
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.device_clk(clk),
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.device_reset(reset),
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.phy_data(phy_data_out),
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.phy_charisk(phy_charisk_out),
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.phy_header(),
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.sysref(sysref_tx),
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.lmfc_edge(tx_lmfc_edge),
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.lmfc_clk(tx_lmfc_clk),
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.sync(sync),
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.tx_data({NUM_LANES{tx_data}}),
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.tx_ready(tx_ready),
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.tx_eof(tx_eof),
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.tx_sof(tx_sof),
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.tx_somf(),
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.tx_eomf(),
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.tx_valid(1'b1),
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.cfg_lanes_disable(tx_cfg_lanes_disable),
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.cfg_links_disable(tx_cfg_links_disable),
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.cfg_octets_per_multiframe(tx_cfg_octets_per_multiframe),
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.cfg_octets_per_frame(tx_cfg_octets_per_frame),
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.cfg_continuous_cgs(tx_cfg_continuous_cgs),
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.cfg_continuous_ilas(tx_cfg_continuous_ilas),
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.cfg_skip_ilas(tx_cfg_skip_ilas),
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.cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas),
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.cfg_disable_char_replacement(tx_cfg_disable_char_replacement),
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.cfg_disable_scrambler(tx_cfg_disable_scrambler),
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.device_cfg_octets_per_multiframe(tx_device_cfg_octets_per_multiframe),
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.device_cfg_octets_per_frame(tx_device_cfg_octets_per_frame),
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.device_cfg_beats_per_multiframe(tx_device_cfg_beats_per_multiframe),
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.device_cfg_lmfc_offset(tx_device_cfg_lmfc_offset),
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.device_cfg_sysref_disable(tx_device_cfg_sysref_disable),
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.device_cfg_sysref_oneshot(tx_device_cfg_sysref_oneshot),
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.ilas_config_rd(tx_ilas_config_rd),
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.ilas_config_addr(tx_ilas_config_addr),
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.ilas_config_data(tx_ilas_config_data),
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.ctrl_manual_sync_request(1'b0),
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.device_event_sysref_edge (tx_event_sysref_edge),
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.device_event_sysref_alignment_error (tx_event_sysref_alignment_error),
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.status_sync (tx_status_sync),
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.status_state (tx_status_state),
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.status_synth_params0(),
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.status_synth_params1(),
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.status_synth_params2()
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);
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wire [NUM_LANES-1:0] rx_cfg_lanes_disable;
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wire [NUM_LINKS-1:0] rx_cfg_links_disable;
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wire [9:0] rx_cfg_octets_per_multiframe;
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wire [7:0] rx_cfg_octets_per_frame;
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wire [7:0] rx_device_cfg_lmfc_offset;
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wire [9:0] rx_device_cfg_octets_per_multiframe;
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wire [7:0] rx_device_cfg_octets_per_frame;
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wire [7:0] rx_device_cfg_beats_per_multiframe;
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wire rx_device_cfg_sysref_disable;
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wire rx_device_cfg_sysref_oneshot;
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wire rx_device_cfg_buffer_early_release;
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wire [7:0] rx_device_cfg_buffer_delay;
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wire rx_cfg_disable_scrambler;
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wire rx_cfg_disable_char_replacement;
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wire [NUM_LANES-1:0] rx_status_lane_ifs_ready;
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wire [NUM_LANES*14-1:0] rx_status_lane_latency;
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wire [NUM_LANES*8-1:0] rx_status_lane_frame_align_err_cnt;
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wire [7:0] rx_cfg_frame_align_err_threshold;
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wire [32*NUM_LANES-1:0] rx_status_err_statistics_cnt;
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wire rx_lmfc_edge;
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wire rx_lmfc_clk;
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wire rx_event_sysref_alignment_error;
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wire rx_event_sysref_edge;
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wire [NUM_LANES-1:0] rx_ilas_config_valid;
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wire [NUM_LANES*2-1:0] rx_ilas_config_addr;
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wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] rx_ilas_config_data;
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wire [1:0] rx_status_ctrl_state;
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wire [2*NUM_LANES-1:0] rx_status_lane_cgs_state;
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wire rx_phy_en_char_align;
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jesd204_rx_static_config #(
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS),
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.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
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.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME),
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.SCR(ENABLE_SCRAMBLER),
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.BUFFER_EARLY_RELEASE(BUFFER_EARLY_RELEASE),
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.LINK_MODE(1),
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.SYSREF_DISABLE(SYSREF_DISABLE),
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.SYSREF_ONE_SHOT(SYSREF_ONE_SHOT),
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
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.TPL_DATA_PATH_WIDTH(DATA_PATH_WIDTH)
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) i_rx_cfg (
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.clk(clk),
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.cfg_lanes_disable(rx_cfg_lanes_disable),
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.cfg_links_disable(rx_cfg_links_disable),
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.cfg_octets_per_multiframe(rx_cfg_octets_per_multiframe),
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.cfg_octets_per_frame(rx_cfg_octets_per_frame),
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.cfg_disable_scrambler(rx_cfg_disable_scrambler),
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.cfg_disable_char_replacement(rx_cfg_disable_char_replacement),
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.cfg_frame_align_err_threshold(rx_cfg_frame_align_err_threshold),
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.device_cfg_octets_per_multiframe(rx_device_cfg_octets_per_multiframe),
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.device_cfg_octets_per_frame(rx_device_cfg_octets_per_frame),
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.device_cfg_beats_per_multiframe(rx_device_cfg_beats_per_multiframe),
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.device_cfg_lmfc_offset(rx_device_cfg_lmfc_offset),
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.device_cfg_sysref_disable(rx_device_cfg_sysref_disable),
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.device_cfg_sysref_oneshot(rx_device_cfg_sysref_oneshot),
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.device_cfg_buffer_early_release(rx_device_cfg_buffer_early_release),
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.device_cfg_buffer_delay(rx_device_cfg_buffer_delay)
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);
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jesd204_rx #(
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS),
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.NUM_INPUT_PIPELINE(1),
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.LINK_MODE(1),
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
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.ENABLE_FRAME_ALIGN_CHECK(1),
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.ENABLE_FRAME_ALIGN_ERR_RESET(1),
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.TPL_DATA_PATH_WIDTH(DATA_PATH_WIDTH),
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.ASYNC_CLK(0),
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.ENABLE_CHAR_REPLACE(1)
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) i_rx (
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.clk(clk),
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.reset(reset),
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.device_clk(clk),
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.device_reset(reset),
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.phy_data(phy_data_in),
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.phy_header({2*NUM_LANES{1'b0}}),
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.phy_charisk(phy_charisk_in),
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.phy_notintable({NUM_LANES*DATA_PATH_WIDTH{1'b0}}),
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|
.phy_disperr({NUM_LANES*DATA_PATH_WIDTH{1'b0}}),
|
|
.phy_block_sync({NUM_LANES{1'b0}}),
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|
|
|
.sysref(sysref_rx),
|
|
.lmfc_edge(rx_lmfc_edge),
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|
.lmfc_clk(rx_lmfc_clk),
|
|
|
|
.device_event_sysref_alignment_error(rx_event_sysref_alignment_error),
|
|
.device_event_sysref_edge(rx_event_sysref_edge),
|
|
.event_frame_alignment_error(),
|
|
.event_unexpected_lane_state_error(),
|
|
|
|
.sync(sync),
|
|
|
|
.phy_en_char_align(rx_phy_en_char_align),
|
|
|
|
.rx_data(rx_data),
|
|
.rx_valid(rx_valid),
|
|
.rx_eof(rx_eof),
|
|
.rx_sof(rx_sof),
|
|
.rx_eomf(),
|
|
.rx_somf(),
|
|
|
|
.cfg_lanes_disable(rx_cfg_lanes_disable),
|
|
.cfg_links_disable(rx_cfg_links_disable),
|
|
.cfg_octets_per_multiframe(rx_cfg_octets_per_multiframe),
|
|
.cfg_octets_per_frame(rx_cfg_octets_per_frame),
|
|
.cfg_disable_char_replacement(rx_cfg_disable_char_replacement),
|
|
.cfg_disable_scrambler(rx_cfg_disable_scrambler),
|
|
|
|
.device_cfg_octets_per_multiframe(rx_device_cfg_octets_per_multiframe),
|
|
.device_cfg_octets_per_frame(rx_device_cfg_octets_per_frame),
|
|
.device_cfg_beats_per_multiframe(rx_device_cfg_beats_per_multiframe),
|
|
.device_cfg_lmfc_offset(rx_device_cfg_lmfc_offset),
|
|
.device_cfg_sysref_disable(rx_device_cfg_sysref_disable),
|
|
.device_cfg_sysref_oneshot(rx_device_cfg_sysref_oneshot),
|
|
.device_cfg_buffer_early_release(rx_device_cfg_buffer_early_release),
|
|
.device_cfg_buffer_delay(rx_device_cfg_buffer_delay),
|
|
|
|
.ctrl_err_statistics_reset(1'b0),
|
|
.ctrl_err_statistics_mask(7'b0),
|
|
|
|
.cfg_frame_align_err_threshold(rx_cfg_frame_align_err_threshold),
|
|
|
|
.status_err_statistics_cnt(rx_status_err_statistics_cnt),
|
|
|
|
.ilas_config_valid(rx_ilas_config_valid),
|
|
.ilas_config_addr(rx_ilas_config_addr),
|
|
.ilas_config_data(rx_ilas_config_data),
|
|
|
|
.status_ctrl_state(rx_status_ctrl_state),
|
|
.status_lane_cgs_state(rx_status_lane_cgs_state),
|
|
|
|
.status_lane_ifs_ready(rx_status_lane_ifs_ready),
|
|
.status_lane_latency(rx_status_lane_latency),
|
|
.status_lane_emb_state(),
|
|
.status_lane_frame_align_err_cnt(rx_status_lane_frame_align_err_cnt),
|
|
|
|
.status_synth_params0(),
|
|
.status_synth_params1(),
|
|
.status_synth_params2()
|
|
);
|
|
|
|
always @(posedge clk) begin
|
|
if (reset == 1'b1) begin
|
|
data_mismatch <= 1'b0;
|
|
end else if (rx_valid == 1'b1) begin
|
|
if ((rx_data & rx_mask) !== ({NUM_LANES{rx_ref_data}} & rx_mask)) begin
|
|
data_mismatch <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
reg [NUM_LANES-1:0] lane_latency_match;
|
|
|
|
generate for (i = 0; i < NUM_LANES; i = i + 1) begin
|
|
wire [31:0] LANE_OFFSET = BASE_LATENCY + LANE_DELAY + BEATS_PER_MULTIFRAME + i;
|
|
|
|
always @(posedge clk) begin
|
|
if (rx_status_lane_ifs_ready[i] == 1'b1 &&
|
|
rx_status_lane_latency[i*14+13:i*14+DPW_LOG2] == LANE_OFFSET) begin
|
|
lane_latency_match[i] <= 1'b1;
|
|
end else begin
|
|
lane_latency_match[i] <= 1'b0;
|
|
end
|
|
end
|
|
end endgenerate
|
|
|
|
always @(*) begin
|
|
if (rx_valid !== 1'b1 || tx_ready !== 1'b1 || data_mismatch == 1'b1 ||
|
|
&lane_latency_match != 1'b1) begin
|
|
failed <= 1'b1;
|
|
end else begin
|
|
failed <= 1'b0;
|
|
end
|
|
end
|
|
endmodule
|