Lars-Peter Clausen 324c0528c2 fmcomms6: Better cope with higher sample rates ... There can be a rather high latency between the last byte of a burst has been send and the time the response for the burst is received. Running at high samplerates this can cause the internal DMA store and forward FIFO to fill up and subsequently stall the DMA pipeline and drop samples. To better cope with the situation double the size of the internal FIFO. Also increase the clock of the AXI bus to be able to accommodate a samplerate of 310MHz. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2014-12-04 13:28:37 +01:00
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common	fmcomms6: Better cope with higher sample rates	2014-12-04 13:28:37 +01:00
zc706	fmcomms6_fmc: Update interrupts	2014-11-24 18:23:35 +02:00