Rejeesh Kutty 2a8703763e zc706pr - 706 partial reconfiguration		2015-05-04 12:33:28 -04:00
..
a5gt	a5gt:common: Added phy reset signal from ethernet in pin assignments	2015-01-23 12:31:41 +02:00
a5gte	a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2	2015-01-23 12:30:16 +02:00
a5soc	a5soc: fmcjesdadc1+hdmi version	2014-08-14 09:05:38 -04:00
ac701	AC701: Common, removed system clock constraint	2015-04-02 11:51:20 +03:00
c5soc	projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI.	2014-08-27 21:46:23 +03:00
kc705	kc705/vc707: consistency fixes	2015-03-26 14:00:50 -04:00
kcu105	kcu105: ddr mig rbc to rcb	2015-04-23 15:30:48 -04:00
mitx045	itx045: updates	2015-05-01 16:18:23 -04:00
rfsom	rfsom: sdio 50mhz	2015-04-23 15:30:50 -04:00
vc707	vc707: Changed mig project to use BANK_ROW_COLUMN, as it seems this mode gives best performance	2015-04-28 17:15:58 +03:00
xilinx	util_dacfifo: Update BRAM DAC Fifo	2015-04-21 15:45:56 +03:00
zc702	common: Place HDMI interface registers into the IOB	2015-04-23 14:33:47 +02:00
zc706	common: Place HDMI interface registers into the IOB	2015-04-23 14:33:47 +02:00
zc706pr	zc706pr - 706 partial reconfiguration	2015-05-04 12:33:28 -04:00
zed	common: Place HDMI interface registers into the IOB	2015-04-23 14:33:47 +02:00