128 lines
4.3 KiB
Verilog
128 lines
4.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9680_if (
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// jesd interface
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// rx_clk is (line-rate/40)
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input rx_clk,
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input [ 3:0] rx_sof,
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input [127:0] rx_data,
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// adc data output
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output adc_clk,
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input adc_rst,
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output [55:0] adc_data_a,
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output [55:0] adc_data_b,
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output adc_or_a,
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output adc_or_b,
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output reg adc_status);
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// internal registers
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// internal signals
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wire [15:0] adc_data_a_s3_s;
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wire [15:0] adc_data_a_s2_s;
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wire [15:0] adc_data_a_s1_s;
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wire [15:0] adc_data_a_s0_s;
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wire [15:0] adc_data_b_s3_s;
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wire [15:0] adc_data_b_s2_s;
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wire [15:0] adc_data_b_s1_s;
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wire [15:0] adc_data_b_s0_s;
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wire [127:0] rx_data_s;
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// adc clock is the reference clock
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assign adc_clk = rx_clk;
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assign adc_or_a = 1'b0;
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assign adc_or_b = 1'b0;
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// adc channels
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assign adc_data_a = { adc_data_a_s3_s[13:0], adc_data_a_s2_s[13:0],
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adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]};
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assign adc_data_b = { adc_data_b_s3_s[13:0], adc_data_b_s2_s[13:0],
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adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]};
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// data multiplex
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assign adc_data_a_s3_s = {rx_data_s[ 57: 56], rx_data_s[ 31: 24], rx_data_s[ 63: 58]};
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assign adc_data_a_s2_s = {rx_data_s[ 49: 48], rx_data_s[ 23: 16], rx_data_s[ 55: 50]};
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assign adc_data_a_s1_s = {rx_data_s[ 41: 40], rx_data_s[ 15: 8], rx_data_s[ 47: 42]};
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assign adc_data_a_s0_s = {rx_data_s[ 33: 32], rx_data_s[ 7: 0], rx_data_s[ 39: 34]};
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assign adc_data_b_s3_s = {rx_data_s[121:120], rx_data_s[ 95: 88], rx_data_s[127:122]};
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assign adc_data_b_s2_s = {rx_data_s[113:112], rx_data_s[ 87: 80], rx_data_s[119:114]};
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assign adc_data_b_s1_s = {rx_data_s[105:104], rx_data_s[ 79: 72], rx_data_s[111:106]};
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assign adc_data_b_s0_s = {rx_data_s[ 97: 96], rx_data_s[ 71: 64], rx_data_s[103: 98]};
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// status
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always @(posedge rx_clk) begin
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if (adc_rst == 1'b1) begin
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adc_status <= 1'b0;
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end else begin
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adc_status <= 1'b1;
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end
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end
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// frame-alignment
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genvar n;
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generate
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for (n = 0; n < 4; n = n + 1) begin: g_xcvr_if
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ad_xcvr_rx_if i_xcvr_if (
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.rx_clk (rx_clk),
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.rx_ip_sof (rx_sof),
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.rx_ip_data (rx_data[((n*32)+31):(n*32)]),
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.rx_sof (),
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.rx_data (rx_data_s[((n*32)+31):(n*32)]));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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