pluto_hdl_adi/library/xilinx/axi_xcvrlb
Lars-Peter Clausen de4fe30238 library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
The external s_axi_{awaddr,araddr} signals that are connect to the core
have their width set according to the specified size of the register map.

If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently
is for many cores) the MSBs of those signals are left unconnected, which
generates a warning.

To avoid this make sure that the signal width matches the declared register
map size.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:21:25 +02:00
..
Makefile updated makefiles 2016-12-09 23:06:41 +02:00
axi_xcvrlb.v library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size 2017-08-01 15:21:25 +02:00
axi_xcvrlb_1.v axi_xcvrlb: Fix util_adxcvr_xch instantiation (6d4430) 2017-07-06 13:08:29 +01:00
axi_xcvrlb_constr.xdc constraints: Update constraints 2017-02-24 13:43:32 +02:00
axi_xcvrlb_ip.tcl library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00