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ATofan 2c898bf3a2 Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project 
ZC706 runs rx_clk at 250 MHz.
ZC702 and ZED run rx_clk at 200 MHz due to slower fabric.
The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly.
Both DDS and DMA mode work.
 		2014-03-18 15:27:42 +02:00
library axi_dmac: Fix default value for DMA type 2014-03-17 13:20:49 +01:00
projects Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project 2014-03-18 15:27:42 +02:00
.gitignore added gitignore 2014-03-05 10:47:16 -05:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Update README.md 2014-03-13 14:03:15 -04:00

README.md

hdl

Analog Devices HDL libraries and projects

http://wiki.analog.com/resources/fpga/docs/hdl/github

http://wiki.analog.com/resources/fpga/docs/hdl/regmap