133 lines
4.2 KiB
Verilog
133 lines
4.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// A simple adder/substracter width preconfigured input ports width and turn-around value
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// Output = A - B_constant or A + B_constant
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// Constraints: Awidth >= Bwidth
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`timescale 1ns/1ps
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module ad_addsub (
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clk,
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A,
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Amax,
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out,
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CE
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);
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// parameters
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parameter A_WIDTH = 32;
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parameter CONST_VALUE = 32'h1;
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parameter ADD_SUB = 0;
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localparam ADDER = 0;
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localparam SUBSTRACTER = 1;
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// I/O definitions
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input clk;
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input [(A_WIDTH-1):0] A;
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input [(A_WIDTH-1):0] Amax;
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output [(A_WIDTH-1):0] out;
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input CE;
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// registers
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reg [(A_WIDTH-1):0] out = 'b0;
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reg [A_WIDTH:0] out_d = 'b0;
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reg [A_WIDTH:0] out_d2 = 'b0;
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reg [(A_WIDTH-1):0] A_d = 'b0;
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reg [(A_WIDTH-1):0] A_d2 = 'b0;
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reg [(A_WIDTH-1):0] Amax_d = 'b0;
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reg [(A_WIDTH-1):0] Amax_d2 = 'b0;
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// constant regs
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reg [(A_WIDTH-1):0] B_reg = CONST_VALUE;
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// latch the inputs
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always @(posedge clk) begin
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A_d <= A;
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A_d2 <= A_d;
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Amax_d <= Amax;
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Amax_d2 <= Amax_d;
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end
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// ADDER/SUBSTRACTER
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always @(posedge clk) begin
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if ( ADD_SUB == ADDER ) begin
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out_d <= A_d + B_reg;
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end else begin
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out_d <= A_d - B_reg;
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end
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end
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// Resolve
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always @(posedge clk) begin
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if ( ADD_SUB == ADDER ) begin
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if ( out_d > Amax_d2 ) begin
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out_d2 <= out_d - Amax_d2;
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end else begin
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out_d2 <= out_d;
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end
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end else begin // SUBSTRACTER
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if ( out_d[A_WIDTH] == 1'b1 ) begin
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out_d2 <= Amax_d2 + out_d;
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end else begin
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out_d2 <= out_d;
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end
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end
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end
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// output logic
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always @(posedge clk) begin
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if ( CE ) begin
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out <= out_d2;
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end else begin
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out <= 'b0;
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end
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end
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endmodule
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