117 lines
3.6 KiB
Verilog
117 lines
3.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// Transmit HDMI, CrYCb to RGB conversion
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// The multiplication coefficients are in 1.4.12 format
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// The addition coefficients are in 1.12.12 format
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// R = (+408.583/256)*Cr + (+298.082/256)*Y + ( 000.000/256)*Cb + (-222.921);
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// G = (-208.120/256)*Cr + (+298.082/256)*Y + (-100.291/256)*Cb + (+135.576);
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// B = ( 000.000/256)*Cr + (+298.082/256)*Y + (+516.412/256)*Cb + (-276.836);
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`timescale 1ns/100ps
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module ad_csc_CrYCb2RGB #(
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parameter DELAY_DATA_WIDTH = 16) (
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// Cr-Y-Cb inputs
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input clk,
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input [DELAY_DATA_WIDTH-1:0] CrYCb_sync,
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input [23:0] CrYCb_data,
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// R-G-B outputs
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output [DELAY_DATA_WIDTH-1:0] RGB_sync,
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output [23:0] RGB_data);
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localparam DW = DELAY_DATA_WIDTH - 1;
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// red
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ad_csc #(
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.DELAY_DW (DELAY_DATA_WIDTH),
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.MUL_COEF_DW (18),
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.SUM_COEF_DW (28),
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.YCbCr_2_RGB (1))
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i_csc_R (
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.clk (clk),
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.sync (CrYCb_sync),
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.data (CrYCb_data),
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.C1 ( 18'd52299),
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.C2 ( 18'd38154),
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.C3 ( 18'd0),
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.C4 (-28'd7304675),
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.csc_sync (RGB_sync),
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.csc_data (RGB_data[23:16]));
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// green
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ad_csc #(
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.MUL_COEF_DW (18),
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.SUM_COEF_DW (28),
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.YCbCr_2_RGB (1))
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i_csc_G (
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.clk (clk),
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.sync (1'd0),
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.data (CrYCb_data),
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.C1 (-18'd26639),
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.C2 ( 18'd38154),
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.C3 (-18'd12837),
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.C4 ( 28'd4442554),
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.csc_sync (),
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.csc_data (RGB_data[15:8]));
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// blue
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ad_csc #(
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.MUL_COEF_DW (18),
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.SUM_COEF_DW (28),
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.YCbCr_2_RGB (1))
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i_csc_B (
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.clk (clk),
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.sync (1'd0),
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.data (CrYCb_data),
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.C1 ( 18'd0),
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.C2 ( 18'd38154),
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.C3 ( 18'd66101),
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.C4 (-28'd9071362),
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.csc_sync (),
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.csc_data (RGB_data[7:0]));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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