145 lines
4.5 KiB
Verilog
145 lines
4.5 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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// Constraints:
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// - IN_DATA_PATH_WIDTH >= OUT_DATA_PATH_WIDTH
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//
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module jesd204_tx_gearbox #(
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parameter IN_DATA_PATH_WIDTH = 6,
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parameter OUT_DATA_PATH_WIDTH = 4,
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parameter NUM_LANES = 1,
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parameter DEPTH = 16
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) (
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input link_clk,
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input reset,
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input device_clk,
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input device_reset,
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input [NUM_LANES*IN_DATA_PATH_WIDTH*8-1:0] device_data,
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input device_lmfc_edge,
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output [NUM_LANES*OUT_DATA_PATH_WIDTH*8-1:0] link_data,
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input output_ready
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);
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localparam MEM_W = IN_DATA_PATH_WIDTH*8*NUM_LANES;
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localparam D_LOG2 = $clog2(DEPTH);
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reg [MEM_W-1:0] mem [0:DEPTH-1];
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reg [D_LOG2-1:0] in_addr ='h00;
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reg [D_LOG2-1:0] out_addr = 'b0;
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reg mem_rd_valid = 'b0;
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reg [MEM_W-1:0] mem_rd_data;
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wire mem_wr_en = 1'b1;
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wire mem_rd_en;
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wire [D_LOG2-1:0] in_out_addr;
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wire [D_LOG2-1:0] out_in_addr;
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wire [NUM_LANES-1:0] unpacker_ready;
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wire output_ready_sync;
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sync_bits i_sync_ready (
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.in_bits(output_ready),
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.out_resetn(~device_reset),
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.out_clk(device_clk),
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.out_bits(output_ready_sync)
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);
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always @(posedge device_clk) begin
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if (device_lmfc_edge & ~output_ready_sync) begin
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in_addr <= 'h01;
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end else if (mem_wr_en) begin
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in_addr <= in_addr + 1;
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end
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end
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always @(posedge device_clk) begin
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if (mem_wr_en) begin
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mem[in_addr] <= device_data;
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end
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end
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assign mem_rd_en = output_ready&unpacker_ready[0];
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always @(posedge link_clk) begin
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if (mem_rd_en) begin
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mem_rd_data <= mem[out_addr];
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end
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mem_rd_valid <= mem_rd_en;
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end
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always @(posedge link_clk) begin
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if (reset) begin
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out_addr <= 'b0;
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end else if (mem_rd_en) begin
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out_addr <= out_addr + 1;
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end
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end
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genvar i;
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generate for (i = 0; i < NUM_LANES; i=i+1) begin: unpacker
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ad_upack #(
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.I_W(IN_DATA_PATH_WIDTH),
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.O_W(OUT_DATA_PATH_WIDTH),
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.UNIT_W(8),
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.O_REG(0)
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) i_ad_upack (
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.clk(link_clk),
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.reset(reset),
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.idata(mem_rd_data[i*IN_DATA_PATH_WIDTH*8+:IN_DATA_PATH_WIDTH*8]),
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.ivalid(mem_rd_valid),
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.iready(unpacker_ready[i]),
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.odata(link_data[i*OUT_DATA_PATH_WIDTH*8+:OUT_DATA_PATH_WIDTH*8]),
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.ovalid()
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);
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end
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endgenerate
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endmodule
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