109 lines
4.3 KiB
Verilog
109 lines
4.3 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_tx_header (
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input clk,
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input reset,
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input [1:0] cfg_header_mode,
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input lmc_edge,
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input lmc_quarter_edge,
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// Header content to be sent must be valid during lmc_edge
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input eoemb,
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input [2:0] crc3,
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input [11:0] crc12,
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input [25:0] fec,
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input [18:0] cmd,
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output [1:0] header
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);
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reg header_bit;
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reg [31:0] sync_word = 'h0;
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always @(posedge clk) begin
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if (reset) begin
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sync_word <= 'h0;
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end else if (lmc_edge) begin
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case (cfg_header_mode)
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// CRC-12
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2'b00 : sync_word <= {crc12[11:9],1'b1,crc12[8:6],1'b1,
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crc12[5:3],1'b1,crc12[2:0],1'b1,
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cmd[6:4],1'b1,cmd[3],1'b1,eoemb,1'b1,
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cmd[2:0],5'b00001};
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// CRC-3
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2'b01 : sync_word <= { crc3[2:0],1'b1,cmd[6:4],1'b1,
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3'b000,1'b1,cmd[3:1],1'b1,
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3'b000,1'b1,cmd[0],1'b1,eoemb,1'b1,
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3'b000,5'b00001};
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// FEC
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2'b10 : sync_word <= { fec[25:18],
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fec[17:10],
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fec[9:4],eoemb,fec[3],
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fec[2:0],5'b00001};
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// Stand alone command
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2'b11 : sync_word <= { cmd[18:16],1'b1,cmd[15:13],1'b1,
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cmd[12:10],1'b1,cmd[9:7],1'b1,
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cmd[6:4],1'b1,cmd[3],1'b1,eoemb,1'b1,
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cmd[2:0],5'b00001};
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endcase
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end else begin
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if (lmc_quarter_edge && cfg_header_mode == 2'b01) begin
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sync_word <= {crc3[2],crc3[1],crc3[0],sync_word[27:0],1'b0};
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end else begin
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sync_word <= {sync_word[30:0],1'b0};
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end
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end
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end
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assign header = {~sync_word[31],sync_word[31]};
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endmodule
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