zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
3,024 Commits
1 Branch
0 Tags
23 MiB
Verilog 61.7%
Tcl 31.2%
Makefile 3.5%
VHDL 1.9%
SystemVerilog 1%
Other 0.6%
 
 
 
 
 
 
Go to file
Adrian Costina 2d307d5f58 a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design 2016-09-24 10:06:35 +03:00
library library- dac parameter changes 2016-09-23 16:15:59 -04:00
projects a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design 2016-09-24 10:06:35 +03:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Update .gitignore file 2016-03-16 09:18:49 +02:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-03-31 19:42:52 +03:00

README.md

HDL Reference Designs

Analog Devices Inc. HDL libraries and projects

Branches

Each release has its own branch and master always synced with the latest release. To find out more information about the latest release please check the release notes. Every branch, which has dev in its name, is a development branch and should handle it accordingly.

Latest Release Notes

HDL User Guide

HDL Help & Support