8885caab13
In the current form, when connecting a master to the HP ports all available slave address spaces are mapped to the master (DDR_*, PCIE*, OCM, QSPI) Let the PL masters have access only to the DDR_LOW and DDR_HIGH address spaces to avoid unnecessary resource usage and increase timing margin. |
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| .. | ||
| adi_board.tcl | ||
| adi_env.tcl | ||
| adi_make.tcl | ||
| adi_make_boot_bin.tcl | ||
| adi_project.tcl | ||
| adi_project_alt.tcl | ||
| adi_tquest.tcl | ||
| adi_xilinx_msg.tcl | ||
| project-altera.mk | ||
| project-toplevel.mk | ||
| project-xilinx.mk | ||