198 lines
6.3 KiB
Verilog
198 lines
6.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout [14:0] gpio_bd,
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output hdmi_out_clk,
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output hdmi_vsync,
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output hdmi_hsync,
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output hdmi_data_e,
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output [23:0] hdmi_data,
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output spdif,
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inout iic_scl,
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inout iic_sda,
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input dac_clk_in_p,
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input dac_clk_in_n,
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output dac_clk_out_p,
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output dac_clk_out_n,
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output [13:0] dac_data_out_a_p,
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output [13:0] dac_data_out_a_n,
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output [13:0] dac_data_out_b_p,
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output [13:0] dac_data_out_b_n,
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output spi_csn_clk,
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output spi_csn_dac,
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output spi_clk,
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output spi_mosi,
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input spi_miso);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [ 2:0] spi0_csn;
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wire spi0_clk;
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wire spi0_mosi;
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wire spi0_miso;
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wire [ 2:0] spi1_csn;
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wire spi1_clk;
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wire spi1_mosi;
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wire spi1_miso;
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// assignments
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assign spi_csn_clk = spi0_csn[0];
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assign spi_csn_dac = spi0_csn[1];
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assign spi_clk = spi0_clk;
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assign spi_mosi = spi0_mosi;
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assign spi0_miso = spi_miso;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
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.dio_t (gpio_t[14:0]),
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.dio_i (gpio_o[14:0]),
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.dio_o (gpio_i[14:0]),
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.dio_p (gpio_bd));
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.dac_clk_in_n (dac_clk_in_n),
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.dac_clk_in_p (dac_clk_in_p),
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.dac_clk_out_n (dac_clk_out_n),
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.dac_clk_out_p (dac_clk_out_p),
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.dac_data_out_a_n (dac_data_out_a_n),
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.dac_data_out_a_p (dac_data_out_a_p),
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.dac_data_out_b_n (dac_data_out_b_n),
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.dac_data_out_b_p (dac_data_out_b_p),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
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.ps_intr_07 (1'b0),
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.ps_intr_08 (1'b0),
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.ps_intr_09 (1'b0),
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.ps_intr_10 (1'b0),
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.ps_intr_11 (1'b0),
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.ps_intr_13 (1'b0),
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.spdif (spdif),
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.spi0_clk_i (spi0_clk),
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.spi0_clk_o (spi0_clk),
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.spi0_csn_0_o (spi0_csn[0]),
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.spi0_csn_1_o (spi0_csn[1]),
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.spi0_csn_2_o (spi0_csn[2]),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (spi0_miso),
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.spi0_sdo_i (spi0_mosi),
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.spi0_sdo_o (spi0_mosi),
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.spi1_clk_i (spi1_clk),
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.spi1_clk_o (spi1_clk),
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.spi1_csn_0_o (spi1_csn[0]),
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.spi1_csn_1_o (spi1_csn[1]),
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.spi1_csn_2_o (spi1_csn[2]),
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b1),
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.spi1_sdo_i (spi1_mosi),
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.spi1_sdo_o (spi1_mosi));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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