| .. |
|
a5gt
|
fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
|
2017-02-17 15:21:33 -05:00 |
|
a5gte
|
a5gte: Fixed timing violations
|
2016-12-13 10:30:24 +02:00 |
|
a5soc
|
common/a5soc- device can not run at 100M cpu clock
|
2016-11-08 15:19:23 -05:00 |
|
a10gx
|
a10gx- ignore preliminary timing model warnings
|
2017-03-21 10:52:28 -04:00 |
|
a10soc
|
altera- ignore preliminary timing messages
|
2017-03-20 12:48:53 -04:00 |
|
ac701
|
common/ac701: Connect axi_ddr_cntrl/device_temp_i to GND
|
2016-12-09 13:54:39 +02:00 |
|
altera
|
altera- ignore preliminary timing messages
|
2017-03-20 12:48:53 -04:00 |
|
c5soc
|
arradio/c5soc- remove qsys files
|
2017-03-20 15:56:07 -04:00 |
|
kc705
|
daq2/all - warnings fix
|
2016-08-17 10:36:00 -04:00 |
|
kcu105
|
kcu105- added missing ethernet configurations
|
2017-01-23 10:14:09 -05:00 |
|
microzed
|
common: microzed: Add clock, reset and interrupt support
|
2016-01-13 20:32:26 +01:00 |
|
mitx045
|
version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2
|
2016-08-29 09:50:46 +03:00 |
|
vc707
|
common/vc707- 2016.2 version
|
2016-08-17 10:36:19 -04:00 |
|
xilinx
|
common: adc/dac fifo board designs
|
2017-02-27 16:06:39 -05:00 |
|
zc702
|
version_upgrade: Common ZC702 get an upgrade to 2016.2
|
2016-08-26 10:20:04 +03:00 |
|
zc706
|
common: adc/dac fifo board designs
|
2017-02-27 16:06:39 -05:00 |
|
zcu102
|
zcu102/*- actual clock == desired clock
|
2017-02-06 12:53:47 -05:00 |
|
zed
|
version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2
|
2016-08-29 09:50:46 +03:00 |
|
Makefile
|
Makefiles: Updated Makefiles
|
2015-10-23 10:44:27 +03:00 |
2e22ce3b62