496 lines
20 KiB
VHDL
496 lines
20 KiB
VHDL
----------------------------------------------------------------------
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---- ----
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---- WISHBONE SPDIF IP Core ----
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---- ----
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---- This file is part of the SPDIF project ----
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---- http://www.opencores.org/cores/spdif_interface/ ----
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---- ----
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---- Description ----
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---- SPDIF transmitter signal encoder. Reads out samples from the ----
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---- sample buffer, assembles frames and subframes and encodes ----
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---- serial data as bi-phase mark code. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Geir Drange, gedra@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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--
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity tx_encoder is
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generic (DATA_WIDTH: integer range 16 to 32 := 32);
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port (
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up_clk: in std_logic; -- clock
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data_clk : in std_logic; -- data clock
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resetn : in std_logic; -- resetn
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conf_mode: in std_logic_vector(3 downto 0); -- sample format
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conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
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conf_txdata: in std_logic; -- sample data enable
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conf_txen: in std_logic; -- spdif signal enable
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chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
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chstat_gstat: in std_logic; -- generation status
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chstat_preem: in std_logic; -- preemphasis status
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chstat_copy: in std_logic; -- copyright bit
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chstat_audio: in std_logic; -- data format
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sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
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sample_data_ack: out std_logic; -- sample buffer read
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channel: out std_logic;
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spdif_tx_o: out std_logic);
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end tx_encoder;
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architecture rtl of tx_encoder is
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signal spdif_clk_en, spdif_out : std_logic;
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signal clk_cnt : integer range 0 to 511;
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type buf_states is (IDLE, READ_CHA, READ_CHB, CHA_RDY, CHB_RDY);
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signal bufctrl : buf_states;
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signal cha_samp_ack, chb_samp_ack : std_logic;
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type frame_states is (IDLE, BLOCK_START, CHANNEL_A, CHANNEL_B);
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signal framest : frame_states;
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signal frame_cnt : integer range 0 to 191;
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signal bit_cnt, par_cnt : integer range 0 to 31;
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signal inv_preamble, toggle, valid : std_logic;
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signal def_user_data, def_ch_status : std_logic_vector(191 downto 0);
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signal active_user_data, active_ch_status : std_logic_vector(191 downto 0);
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signal audio : std_logic_vector(23 downto 0);
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signal par_vector : std_logic_vector(26 downto 0);
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signal send_audio : std_logic;
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signal cdc_sync_stage0_tick_counter : std_logic := '0';
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signal cdc_sync_stage1_tick_counter : std_logic := '0';
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signal cdc_sync_stage2_tick_counter : std_logic := '0';
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signal cdc_sync_stage3_tick_counter : std_logic := '0';
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signal tick_counter : std_logic;
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constant X_PREAMBLE : std_logic_vector(0 to 7) := "11100010";
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constant Y_PREAMBLE : std_logic_vector(0 to 7) := "11100100";
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constant Z_PREAMBLE : std_logic_vector(0 to 7) := "11101000";
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function encode_bit (
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signal bit_cnt : integer; -- sub-frame bit position
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signal valid : std_logic; -- validity bit
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signal frame_cnt : integer; -- frame counter
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signal par_cnt : integer; -- parity counter
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signal user_data : std_logic_vector(191 downto 0);
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signal ch_status : std_logic_vector(191 downto 0);
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signal audio : std_logic_vector(23 downto 0);
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signal toggle : std_logic;
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signal prev_spdif : std_logic) -- prev. value of spdif signal
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return std_logic is
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variable spdif, next_bit : std_logic;
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begin
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if bit_cnt > 3 and bit_cnt < 28 then -- audio part
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next_bit := audio(bit_cnt - 4);
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elsif bit_cnt = 28 then -- validity bit
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next_bit := valid;
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elsif bit_cnt = 29 then -- user data
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next_bit := user_data(frame_cnt);
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elsif bit_cnt = 30 then
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next_bit := ch_status(frame_cnt); -- channel status
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elsif bit_cnt = 31 then
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if par_cnt mod 2 = 1 then
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next_bit := '1';
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else
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next_bit := '0';
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end if;
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end if;
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-- bi-phase mark encoding:
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if next_bit = '0' then
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if toggle = '0' then
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spdif := not prev_spdif;
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else
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spdif := prev_spdif;
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end if;
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else
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spdif := not prev_spdif;
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end if;
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return(spdif);
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end encode_bit;
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begin
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-- SPDIF clock enable generation. The clock is a fraction of the data clock,
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-- determined by the conf_ratio value.
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DCLK : process (data_clk)
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begin
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if rising_edge(data_clk) then
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cdc_sync_stage0_tick_counter <= not cdc_sync_stage0_tick_counter;
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end if;
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end process DCLK;
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process (up_clk) begin
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if rising_edge(up_clk) then
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cdc_sync_stage1_tick_counter <= cdc_sync_stage0_tick_counter;
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cdc_sync_stage2_tick_counter <= cdc_sync_stage1_tick_counter;
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cdc_sync_stage3_tick_counter <= cdc_sync_stage2_tick_counter;
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end if;
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end process;
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tick_counter <= cdc_sync_stage3_tick_counter xor cdc_sync_stage2_tick_counter;
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CGEN: process (up_clk)
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begin
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if rising_edge(up_clk) then
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if resetn = '0' or conf_txen = '0' then
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clk_cnt <= 0;
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spdif_clk_en <= '0';
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else
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spdif_clk_en <= '0';
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if tick_counter = '1' then
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if clk_cnt < to_integer(unsigned(conf_ratio)) then
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clk_cnt <= clk_cnt + 1;
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else
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clk_cnt <= 0;
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spdif_clk_en <= '1';
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end if;
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end if;
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end if;
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end if;
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end process CGEN;
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SRD: process (up_clk)
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begin
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if rising_edge(up_clk) then
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if resetn = '0' or conf_txdata = '0' then
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bufctrl <= IDLE;
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sample_data_ack <= '0';
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channel <= '0';
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else
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case bufctrl is
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when IDLE =>
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sample_data_ack <= '0';
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if conf_txdata = '1' then
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bufctrl <= READ_CHA;
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sample_data_ack <='1';
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end if;
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when READ_CHA =>
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channel <= '0';
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sample_data_ack <= '0';
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bufctrl <= CHA_RDY;
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when CHA_RDY =>
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if cha_samp_ack = '1' then
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sample_data_ack <= '1';
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bufctrl <= READ_CHB;
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end if;
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when READ_CHB =>
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channel <= '1';
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sample_data_ack <= '0';
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bufctrl <= CHB_RDY;
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when CHB_RDY =>
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if chb_samp_ack = '1' then
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sample_data_ack <= '1';
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bufctrl <= READ_CHA;
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end if;
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when others =>
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bufctrl <= IDLE;
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end case;
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end if;
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end if;
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end process SRD;
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TXSYNC: process (data_clk)
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begin
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if (rising_edge(data_clk)) then
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spdif_tx_o <= spdif_out;
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end if;
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end process TXSYNC;
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-- State machine that generates sub-frames and blocks
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FRST: process (up_clk)
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begin
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if rising_edge(up_clk) then
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if resetn = '0' or conf_txen = '0' then
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framest <= IDLE;
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frame_cnt <= 0;
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bit_cnt <= 0;
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spdif_out <= '0';
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inv_preamble <= '0';
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toggle <= '0';
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valid <= '1';
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send_audio <= '0';
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cha_samp_ack <= '0';
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chb_samp_ack <= '0';
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else
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if spdif_clk_en = '1' then -- SPDIF clock is twice the bit rate
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case framest is
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when IDLE =>
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bit_cnt <= 0;
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frame_cnt <= 0;
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inv_preamble <= '0';
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toggle <= '0';
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framest <= BLOCK_START;
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when BLOCK_START => -- Start of channels status block/Ch. A
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chb_samp_ack <= '0';
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toggle <= not toggle; -- Each bit uses two clock enables,
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if toggle = '1' then -- counted by the toggle bit.
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if bit_cnt < 31 then
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bit_cnt <= bit_cnt + 1;
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else
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bit_cnt <= 0;
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if send_audio = '1' then
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cha_samp_ack <= '1';
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end if;
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framest <= CHANNEL_B;
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end if;
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end if;
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-- Block start uses preamble Z.
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if bit_cnt < 4 then
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if toggle = '0' then
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spdif_out <= Z_PREAMBLE(2 * bit_cnt) xor inv_preamble;
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else
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spdif_out <= Z_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
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end if;
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par_cnt <= 0;
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elsif bit_cnt > 3 and bit_cnt <= 31 then
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spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
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par_cnt, active_user_data,
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active_ch_status,
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audio, toggle, spdif_out);
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if bit_cnt = 31 then
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inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
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par_cnt, active_user_data,
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active_ch_status,
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audio, toggle, spdif_out);
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end if;
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if toggle = '0' then
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if bit_cnt > 3 and bit_cnt < 31 and
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par_vector(bit_cnt - 4) = '1' then
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par_cnt <= par_cnt + 1;
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end if;
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end if;
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end if;
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when CHANNEL_A => -- Sub-frame: channel A.
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chb_samp_ack <= '0';
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toggle <= not toggle;
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if toggle = '1' then
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if bit_cnt < 31 then
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bit_cnt <= bit_cnt + 1;
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else
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bit_cnt <= 0;
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if spdif_out = '1' then
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inv_preamble <= '1';
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else
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inv_preamble <= '0';
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end if;
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if send_audio = '1' then
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cha_samp_ack <= '1';
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end if;
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framest <= CHANNEL_B;
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end if;
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end if;
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-- Channel A uses preable X.
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if bit_cnt < 4 then
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if toggle = '0' then
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spdif_out <= X_PREAMBLE(2 * bit_cnt) xor inv_preamble;
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else
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spdif_out <= X_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
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end if;
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par_cnt <= 0;
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elsif bit_cnt > 3 and bit_cnt <= 31 then
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spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
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par_cnt, active_user_data,
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active_ch_status,
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audio, toggle, spdif_out);
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if bit_cnt = 31 then
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inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
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par_cnt, active_user_data,
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active_ch_status,
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audio, toggle, spdif_out);
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end if;
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if toggle = '0' then
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if bit_cnt > 3 and bit_cnt < 31 and
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par_vector(bit_cnt - 4) = '1' then
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par_cnt <= par_cnt + 1;
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end if;
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end if;
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end if;
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when CHANNEL_B => -- Sub-frame: channel B.
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cha_samp_ack <= '0';
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toggle <= not toggle;
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if toggle = '1' then
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if bit_cnt < 31 then
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bit_cnt <= bit_cnt + 1;
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else
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bit_cnt <= 0;
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valid <= not conf_txdata;
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if spdif_out = '1' then
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inv_preamble <= '1';
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else
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inv_preamble <= '0';
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end if;
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send_audio <= conf_txdata; -- 1 if audio samples sohuld be sent
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if send_audio = '1' then
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chb_samp_ack <= '1';
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end if;
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if frame_cnt < 191 then -- One block is 192 frames
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frame_cnt <= frame_cnt + 1;
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framest <= CHANNEL_A;
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else
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frame_cnt <= 0;
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framest <= BLOCK_START;
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end if;
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end if;
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end if;
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-- Channel B uses preable Y.
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if bit_cnt < 4 then
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if toggle = '0' then
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spdif_out <= Y_PREAMBLE(2 * bit_cnt) xor inv_preamble;
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else
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spdif_out <= Y_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
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end if;
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par_cnt <= 0;
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elsif bit_cnt > 3 and bit_cnt <= 31 then
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spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
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par_cnt, active_user_data,
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active_ch_status,
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audio, toggle, spdif_out);
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if bit_cnt = 31 then
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inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
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par_cnt, active_user_data,
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active_ch_status,
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audio, toggle, spdif_out);
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end if;
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if toggle = '0' then
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if bit_cnt > 3 and bit_cnt < 31 and
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par_vector(bit_cnt - 4) = '1' then
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par_cnt <= par_cnt + 1;
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end if;
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end if;
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end if;
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when others =>
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framest <= IDLE;
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end case;
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end if;
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end if;
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end if;
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end process FRST;
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-- Audio data latching
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DA32: if DATA_WIDTH = 32 generate
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ALAT: process (up_clk)
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begin
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if rising_edge(up_clk) then
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if send_audio = '0' then
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audio(23 downto 0) <= (others => '0');
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else
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case to_integer(unsigned(conf_mode)) is
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when 0 => -- 16 bit audio
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audio(23 downto 8) <= sample_data(15 downto 0);
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audio(7 downto 0) <= (others => '0');
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when 1 => -- 17 bit audio
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audio(23 downto 7) <= sample_data(16 downto 0);
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audio(6 downto 0) <= (others => '0');
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when 2 => -- 18 bit audio
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audio(23 downto 6) <= sample_data(17 downto 0);
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audio(5 downto 0) <= (others => '0');
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when 3 => -- 19 bit audio
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audio(23 downto 5) <= sample_data(18 downto 0);
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audio(4 downto 0) <= (others => '0');
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when 4 => -- 20 bit audio
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audio(23 downto 4) <= sample_data(19 downto 0);
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audio(3 downto 0) <= (others => '0');
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when 5 => -- 21 bit audio
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audio(23 downto 3) <= sample_data(20 downto 0);
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audio(2 downto 0) <= (others => '0');
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when 6 => -- 22 bit audio
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audio(23 downto 2) <= sample_data(21 downto 0);
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audio(1 downto 0) <= (others => '0');
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when 7 => -- 23 bit audio
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audio(23 downto 1) <= sample_data(22 downto 0);
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audio(0) <= '0';
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when 8 => -- 24 bit audio
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audio(23 downto 0) <= sample_data(23 downto 0);
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when others => -- unsupported modes
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audio(23 downto 0) <= (others => '0');
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end case;
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end if;
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end if;
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end process ALAT;
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end generate DA32;
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DA16: if DATA_WIDTH = 16 generate
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ALAT: process (up_clk)
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begin
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if rising_edge(up_clk) then
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if send_audio = '0' then
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audio(23 downto 0) <= (others => '0');
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else
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audio(23 downto 8) <= sample_data(15 downto 0);
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audio(7 downto 0) <= (others => '0');
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end if;
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end if;
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end process ALAT;
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end generate DA16;
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-- Parity vector. These bits are counted to generate even parity
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par_vector(23 downto 0) <= audio(23 downto 0);
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par_vector(24) <= valid;
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par_vector(25) <= active_user_data(frame_cnt);
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par_vector(26) <= active_ch_status(frame_cnt);
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-- Channel status and user datat to be used if buffers are disabled.
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-- User data is then all zero, while channel status bits are taken from
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-- register TxChStat.
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def_user_data(191 downto 0) <= (others => '0');
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def_ch_status(0) <= '0'; -- consumer mode
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def_ch_status(1) <= chstat_audio; -- audio bit
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def_ch_status(2) <= chstat_copy; -- copy right
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def_ch_status(5 downto 3) <= "000" when chstat_preem = '0'
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else "001"; -- pre-emphasis
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def_ch_status(7 downto 6) <= "00";
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def_ch_status(14 downto 8) <= (others => '0');
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def_ch_status(15) <= chstat_gstat; -- generation status
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def_ch_status(23 downto 16) <= (others => '0');
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def_ch_status(27 downto 24) <= "0000" when chstat_freq = "00" else
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"0010" when chstat_freq = "01" else
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"0011" when chstat_freq = "10" else
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"0001";
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def_ch_status(191 downto 28) <= (others => '0'); --191 28
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-- Generate channel status vector based on configuration register setting.
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active_ch_status <= def_ch_status;
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-- Generate user data vector based on configuration register setting.
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active_user_data <= def_user_data;
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|
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end rtl;
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