2eaf931e07
The MMCM generating the logic analyzer clock unfortunately consumes a disproportionately large amount of power compared to the rest of the design. Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs. The IO PLL is running anyway so the power requirement is much lower. For the time being this means we loose the ability to source the clock from an external pin. But that feature is not supported by software at the moment anyway. We'll bring it eventually when required. This changes reduces power consumption by roughly 100mW. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| Makefile | ||
| system_bd.tcl | ||
| system_constr.xdc | ||
| system_project.tcl | ||
| system_top.v | ||