Iulia Moldovan 2f35ce8a51 check_guideline.py: Change copyright format checker ... * Added copyright and license header * Updated files on which it runs on * SystemVerilog not to be supported, since now there are some pkg files that do not have the format of a Verilog file, thus making the checker to fail all the time -- which is not good * Now it can run on files which contain JESD in their paths, because now all of them have the copyright on the same line (but the copyright inside the JESD license can't be checked yet by the script) Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>		2023-07-11 15:12:28 +03:00
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regmap	add: softspan support in adc_channel regmap (#1081)	2023-04-20 19:05:38 +08:00
FMC_eval_board_template.xlsx	docs/FMC_eval_board_template: Update instructions	2023-04-11 11:53:48 +03:00
HDL_logo.png	HDL Logo: Add	2021-09-16 16:49:52 +03:00
HDL_logo.svg	HDL Logo: Add	2021-09-16 16:49:52 +03:00
HDL_logo_w.png	HDL Logo: Add	2021-09-16 16:49:52 +03:00
hdl_coding_guideline.md	check_guideline.py: Change copyright format checker	2023-07-11 15:12:28 +03:00
hdl_pr_process.md	docs: Add HDL PR process documentation	2023-05-30 13:13:15 +03:00