3bf7b6c80f
This IP serves as storage interfacing element for external memories like HBM or DDR4 which have AXI3 or AXI4 data interfaces. The core leverages the axi_dmac as building blocks by merging an array of simplex DMA channels into duplex AXI channels. The core will split the incoming data from the source AXIS interface to multiple AXI channels, and in the read phase will merge the multiple AXI channels into a single AXIS destination interface. The number of duplex channels is set by syntheses parameter and must be set with the ratio of AXIS and AXI3/4 interface. Underflow or Overflow conditions are reported back to the data offload through the control/status interface. In case multiple AXI channels are used the source and destination AXIS interfaces widths must match. |
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