9a91dd8857
* Issue is with ODDR and ODDRE1 inputs D1 and D2 Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com> |
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ad_data_clk.v | ||
ad_data_in.v | ||
ad_data_out.v | ||
ad_dcfilter.v | ||
ad_mmcm_drp.v | ||
ad_mul.v | ||
ad_rst_constr.xdc | ||
ad_serdes_clk.v | ||
ad_serdes_in.v | ||
ad_serdes_out.v | ||
up_clock_mon_constr.xdc | ||
up_xfer_cntrl_constr.xdc | ||
up_xfer_status_constr.xdc |