175 lines
5.4 KiB
Verilog
175 lines
5.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout [14:0] gpio_bd,
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output hdmi_out_clk,
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output hdmi_vsync,
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output hdmi_hsync,
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output hdmi_data_e,
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output [23:0] hdmi_data,
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output spdif,
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inout iic_scl,
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inout iic_sda,
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inout [15:0] adc_db,
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output adc_rd_n,
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output adc_wr_n,
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output adc_cs_n,
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output adc_reset_n,
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output adc_convst,
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input adc_busy,
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output adc_seq_en,
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output [ 1:0] adc_hw_rngsel,
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output [ 2:0] adc_chsel
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);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire adc_db_t;
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wire [15:0] adc_db_o;
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wire [15:0] adc_db_i;
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genvar i;
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// instantiations
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ad_iobuf #(
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.DATA_WIDTH(7)
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) i_iobuf_adc_cntrl (
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.dio_t ({gpio_t[43:41], gpio_t[37], gpio_t[35:33]}),
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.dio_i ({gpio_o[43:41], gpio_o[37], gpio_o[35:33]}),
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.dio_o ({gpio_i[43:41], gpio_i[37], gpio_i[35:33]}),
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.dio_p ({adc_reset_n, // 43
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adc_hw_rngsel, // 42:41
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adc_seq_en, // 37
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adc_chsel})); // 35:33
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generate
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for (i = 0; i < 16; i = i + 1) begin: adc_db_io
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ad_iobuf i_iobuf_adc_db (
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.dio_t(adc_db_t),
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.dio_i(adc_db_o[i]),
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.dio_o(adc_db_i[i]),
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.dio_p(adc_db[i]));
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end
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endgenerate
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ad_iobuf #(
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.DATA_WIDTH(15)
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) i_iobuf_gpio (
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.dio_t(gpio_t[14:0]),
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.dio_i(gpio_o[14:0]),
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.dio_o(gpio_i[14:0]),
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.dio_p(gpio_bd));
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.spdif (spdif),
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.rx_cnvst (adc_convst),
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.rx_cs_n (adc_cs_n),
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.rx_busy (adc_busy),
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.rx_db_o (adc_db_o),
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.rx_db_i (adc_db_i),
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.rx_db_t (adc_db_t),
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.rx_rd_n (adc_rd_n),
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.rx_wr_n (adc_wr_n));
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endmodule
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