Bogdan Luncan 80fe536863 ad9081/vck190/system_project: Change the default profile ... ADC Mode 26: L=8, M=8, S=2, NP=12, LaneRate=24.75 GSPS DAC Mode 24: L=8, M=8, S=2, NP=12, LaneRate=24.75 GSPS Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>		2023-05-16 12:13:55 +03:00
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Makefile	library & projects: Update Makefiles	2023-01-27 11:54:05 +02:00
system_bd.tcl	Updated the makefiles to build the projects in subdirectories based on the build parameters.	2022-11-14 09:38:42 +02:00
system_constr.xdc	ad9081_fmca_ebz/vck190: Make second sync CMOS and GPIO controllable	2022-05-26 09:13:05 +03:00
system_project.tcl	ad9081/vck190/system_project: Change the default profile	2023-05-16 12:13:55 +03:00
system_top.v	ad9081: Proper reset sequence for versal transceivers	2023-05-16 12:13:55 +03:00
timing_constr.xdc	ad9081: Proper reset sequence for versal transceivers	2023-05-16 12:13:55 +03:00