14 lines
655 B
Plaintext
14 lines
655 B
Plaintext
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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# In CMOS mode interface max frequency is 80MHz
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create_clock -period "12.500 ns" -name rx1_clk [get_ports {rx1_dclk_out_p}]
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create_clock -period "12.500 ns" -name rx2_clk [get_ports {rx2_dclk_out_p}]
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create_clock -period "12.500 ns" -name tx1_clk [get_ports {tx1_dclk_out_p}]
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create_clock -period "12.500 ns" -name tx2_clk [get_ports {tx2_dclk_out_p}]
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derive_pll_clocks
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derive_clock_uncertainty
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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