267 lines
8.2 KiB
Verilog
Executable File
267 lines
8.2 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top #(
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parameter NUM_LINKS = 2,
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parameter DEVICE_CODE = 0
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) (
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input sys_rst,
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input sys_clk_p,
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input sys_clk_n,
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input uart_sin,
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output uart_sout,
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output ddr4_act_n,
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output [16:0] ddr4_addr,
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output [ 1:0] ddr4_ba,
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output [ 0:0] ddr4_bg,
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output ddr4_ck_p,
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output ddr4_ck_n,
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output [ 0:0] ddr4_cke,
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output [ 0:0] ddr4_cs_n,
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inout [ 7:0] ddr4_dm_n,
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inout [63:0] ddr4_dq,
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inout [ 7:0] ddr4_dqs_p,
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inout [ 7:0] ddr4_dqs_n,
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output [ 0:0] ddr4_odt,
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output ddr4_reset_n,
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output mdio_mdc,
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inout mdio_mdio,
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input phy_clk_p,
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input phy_clk_n,
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output phy_rst_n,
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input phy_rx_p,
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input phy_rx_n,
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output phy_tx_p,
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output phy_tx_n,
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inout [16:0] gpio_bd,
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output iic_rstn,
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inout iic_scl,
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inout iic_sda,
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input tx_ref_clk_121_p,
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input tx_ref_clk_121_n,
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input tx_ref_clk_126_p,
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input tx_ref_clk_126_n,
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input tx_sysref_p,
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input tx_sysref_n,
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input [ 1:0] tx_sync_p,
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input [ 1:0] tx_sync_n,
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output [ 7:0] tx_data_p,
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output [ 7:0] tx_data_n,
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output spi_csn_dac,
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output spi_csn_clk,
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output spi_csn_clk2,
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input spi_miso,
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output spi_mosi,
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output spi_clk,
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output spi_en,
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inout [ 4:0] dac_ctrl
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);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [ 2:0] spi_csn;
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wire tx_ref_clk;
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wire tx_sysref;
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wire [ 1:0] tx_sync;
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wire tx_sysref_loc;
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assign iic_rstn = 1'b1;
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// spi
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// spi_en is active ...
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// ... high for AD9135-FMC-EBZ, AD9136-FMC-EBZ, AD9144-FMC-EBZ,
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// ... low for AD9171-FMC-EBZ, AD9172-FMC-EBZ, AD9173-FMC-EBZ
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// If you are planning to build a bitstream for just one of those boards you
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// can hardwire the logic level here.
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//
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assign spi_en = (DEVICE_CODE <= 2);
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// 9135/9144/9172 916(1,2,3,4)
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assign spi_csn_dac = spi_csn[1];
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assign spi_csn_clk = spi_csn[0]; // HMC7044 AD9508
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assign spi_csn_clk2 = spi_csn[2]; // NC ADF4355
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/* JESD204 clocks and control signals */
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IBUFDS_GTE4 i_ibufds_tx_ref_clk_121 (
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.CEB (1'd0),
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.I (tx_ref_clk_121_p),
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.IB (tx_ref_clk_121_n),
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.O (tx_ref_clk_121),
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.ODIV2 ());
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IBUFDS_GTE4 i_ibufds_tx_ref_clk_126 (
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.CEB (1'd0),
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.I (tx_ref_clk_126_p),
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.IB (tx_ref_clk_126_n),
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.O (tx_ref_clk_126),
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.ODIV2 ());
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IBUFDS i_ibufds_tx_sysref (
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.I (tx_sysref_p),
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.IB (tx_sysref_n),
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.O (tx_sysref));
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IBUFDS i_ibufds_tx_sync_0 (
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.I (tx_sync_p[0]),
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.IB (tx_sync_n[0]),
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.O (tx_sync[0]));
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IBUFDS i_ibufds_tx_sync_1 (
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.I (tx_sync_p[1]),
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.IB (tx_sync_n[1]),
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.O (tx_sync[1]));
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/* FMC GPIOs */
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ad_iobuf #(
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.DATA_WIDTH(5)
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) i_iobuf (
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.dio_t (gpio_t[21+:5]),
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.dio_i (gpio_o[21+:5]),
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.dio_o (gpio_i[21+:5]),
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.dio_p ({
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dac_ctrl /* 25 - 21 */
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}));
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/*
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* Control signals for different FMC boards:
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*
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* dac_ctrl FMC 9144 like 9162 like 9172 like
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* 0 H13 FMC_TXEN_0 FMC_TXEN_0 FMC_PE_CTRL
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* 1 C10 NC NC FMC_TXEN_0
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* 2 C11 NC NC FMC_TXEN_1
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* 3 H14 FMC_TXEN_1 NC NC
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* 4 D15 NC FMC_HMC849VCTL NC
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*/
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assign dac_fifo_bypass = gpio_o[40];
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/* Board GPIOS. Buttons, LEDs, etc... */
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ad_iobuf #(
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.DATA_WIDTH(17)
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) i_iobuf_bd (
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.dio_t (gpio_t[0+:17]),
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.dio_i (gpio_o[0+:17]),
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.dio_o (gpio_i[0+:17]),
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.dio_p (gpio_bd));
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assign gpio_i[63:26] = gpio_o[63:26];
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assign gpio_i[20:17] = gpio_o[20:17];
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system_wrapper i_system_wrapper (
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.ddr4_act_n (ddr4_act_n),
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.ddr4_adr (ddr4_addr),
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.ddr4_ba (ddr4_ba),
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.ddr4_bg (ddr4_bg),
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.ddr4_ck_c (ddr4_ck_n),
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.ddr4_ck_t (ddr4_ck_p),
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.ddr4_cke (ddr4_cke),
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.ddr4_cs_n (ddr4_cs_n),
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.ddr4_dm_n (ddr4_dm_n),
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.ddr4_dq (ddr4_dq),
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.ddr4_dqs_c (ddr4_dqs_n),
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.ddr4_dqs_t (ddr4_dqs_p),
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.ddr4_odt (ddr4_odt),
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.ddr4_reset_n (ddr4_reset_n),
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.gpio0_i (gpio_i[31:0]),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio1_i (gpio_i[63:32]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio),
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.sgmii_phyclk_clk_n (phy_clk_n),
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.sgmii_phyclk_clk_p (phy_clk_p),
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.phy_rst_n (phy_rst_n),
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.phy_sd (1'b1),
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.sgmii_rxn (phy_rx_n),
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.sgmii_rxp (phy_rx_p),
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.sgmii_txn (phy_tx_n),
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.sgmii_txp (phy_tx_p),
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.spi_clk_i (spi_clk),
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.spi_clk_o (spi_clk),
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.spi_csn_i (spi_csn),
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.spi_csn_o (spi_csn),
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.spi_sdi_i (spi_miso),
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.spi_sdo_i (spi_mosi),
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.spi_sdo_o (spi_mosi),
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.sys_clk_clk_n (sys_clk_n),
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.sys_clk_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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.tx_data_0_n (tx_data_n[0]),
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.tx_data_0_p (tx_data_p[0]),
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.tx_data_1_n (tx_data_n[1]),
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.tx_data_1_p (tx_data_p[1]),
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.tx_data_2_n (tx_data_n[2]),
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.tx_data_2_p (tx_data_p[2]),
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.tx_data_3_n (tx_data_n[3]),
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.tx_data_3_p (tx_data_p[3]),
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.tx_data_4_n (tx_data_n[4]),
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.tx_data_4_p (tx_data_p[4]),
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.tx_data_5_n (tx_data_n[5]),
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.tx_data_5_p (tx_data_p[5]),
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.tx_data_6_n (tx_data_n[6]),
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.tx_data_6_p (tx_data_p[6]),
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.tx_data_7_n (tx_data_n[7]),
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.tx_data_7_p (tx_data_p[7]),
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.tx_ref_clk_0 (tx_ref_clk_126),
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.tx_ref_clk_4 (tx_ref_clk_121),
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.tx_sync_0 (tx_sync),
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.tx_sysref_0 (tx_sysref),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout),
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.dac_fifo_bypass (dac_fifo_bypass));
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// AD9161/2/4-FMC-EBZ works only in single link,
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// The FMC connector instead of SYNC1 has SYSREF connected to it
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assign tx_sysref_loc = (DEVICE_CODE == 3) ? tx_sync[1] : tx_sysref;
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endmodule
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